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2009 Proceedings of ESSCIRC最新文献

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A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS 用于65纳米CMOS GSM系统的0.059 mm2 10.8 mw本地振荡器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326029
S. D. Toso, A. Bevilacqua, M. Tiebout, N. D. Dalt, A. Gerosa, A. Neviani
{"title":"A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS","authors":"S. D. Toso, A. Bevilacqua, M. Tiebout, N. D. Dalt, A. Gerosa, A. Neviani","doi":"10.1109/ESSCIRC.2009.5326029","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326029","url":null,"abstract":"A GSM-compliant local oscillator consuming a tiny die area of only 0.059 mm2 and drawing 9 mA from a 1.2 V supply has been designed in a 65-nm CMOS process using thin-oxide devices only. The system is made of a 13 to 15 GHz LC VCO followed by a divide-by-four injection-locked frequency divider. The divider employs a ring oscillator-based topology leading to a two octave locking range with limited area and power consumption. The phase noise at the output of the system is less than −133 dBc/Hz at 3 MHz offset over the tuning range.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"6 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127954262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop 一个30 mhz, 90 ppm/°C完全集成时钟参考发生器锁频环路
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325940
K. Ueno, T. Asai, Y. Amemiya
{"title":"A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop","authors":"K. Ueno, T. Asai, Y. Amemiya","doi":"10.1109/ESSCIRC.2009.5325940","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325940","url":null,"abstract":"A temperature- and supply-independent clock generator has been developed using 0.35-µm CMOS technology. This generator is based on a simple frequency-locked loop technique and can be implemented monolithically without using LC resonant circuits, quartz resonators, and MEMS oscillators. A sample device that is tunable over a wide frequency range of 2–100 MHz was designed and fabricated. It showed a temperature coefficient of 90 ppm/°C, a line regulation of 4%/V, and a power dissipation of 180 µW, at a frequency of 30 MHz. The process sensitivity (σ/μ) was 2.7%. This clock generator can be used as an on-chip reference clock circuit.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133643923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
25V sampling switch for power management data converters in 0.35µm CMOS with DNMOS 25V采样开关电源管理数据转换器在0.35µm CMOS与DNMOS
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326015
D. Y. Aksin, Ilter Özkaya
{"title":"25V sampling switch for power management data converters in 0.35µm CMOS with DNMOS","authors":"D. Y. Aksin, Ilter Özkaya","doi":"10.1109/ESSCIRC.2009.5326015","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326015","url":null,"abstract":"A new high-voltage bootstrapped sampling switch with input signal range exceeding 11 times its supply voltage is presented. Proposed switch occupies a silicon area of 250µm by 160µm in 0.35µm twin-well CMOS process with drain extended NMOS (DNMOS) capability. The switch safe input signal range is restricted only by the DNMOS drain terminal breakdown voltage, i.e. 50V . Implemented switch can reliably track and hold 20VPP signal on 15VDC at 1MS/s with 2.2V supply without forward biasing any parasitic diode. A designed switched capacitor attenuator utilizing proposed high voltage switch can process 20VPP differential input reliably.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"327 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134465741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 110µW single bit audio continuous-time oversampled converter with 92.5 db dynamic range 一个110µW的单比特音频连续过采样转换器，动态范围为92.5 db
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325953
S. Pavan, P. Sankar
{"title":"A 110µW single bit audio continuous-time oversampled converter with 92.5 db dynamic range","authors":"S. Pavan, P. Sankar","doi":"10.1109/ESSCIRC.2009.5325953","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325953","url":null,"abstract":"The first integrator in a low pass continuous-time ΔΣ modulator normally consumes significant power due to stringent noise and linearity requirements, especially in single-bit designs. We introduce the “assisted opamp integrator” that addresses this problem. The efficacy of our technique is borne out by measurements from a 15 bit audio converter designed in a 0.18 µm CMOS technology. It achieves 92.5 dB dynamic range in a 24 kHz bandwidth and dissipates 110 µW from a 1.8V supply. The Figure of Merit (FOM) of this modulator is 66.5 fJ/level.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115432780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A mixed-signal organic 1kHz comparator with low VT sensitivity on flexible plastic substrate 柔性塑料衬底上低VT灵敏度的混合信号有机1kHz比较器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325942
H. Marien, M. Steyaert, N. Aerle, P. Heremans
{"title":"A mixed-signal organic 1kHz comparator with low VT sensitivity on flexible plastic substrate","authors":"H. Marien, M. Steyaert, N. Aerle, P. Heremans","doi":"10.1109/ESSCIRC.2009.5325942","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325942","url":null,"abstract":"This paper presents a comparator that is designed in an organic electronics technology on a flexible plastic substrate with p-type organic thin-film transistors (p-OTFT) only. The comparator has a gain of 12dB and works at a supply voltage of 20V consuming 9µA. At a clock frequency of 1kHz the input sensitivity is 200mV. The comparator is designed following a threshold-voltage VT insensitive strategy for analog and mixed-signal design in a way to get round VT variations of the pentacene based organic electronics technology. Measurements have been done in ambient environment. The circuits still function well after several weeks of exposure to ambient environment. This comparator can serve in organic smart sensor systems as an interface between analog sensor signals and digital circuitry or as a building block for more complex A-to-D converters.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128164961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS 2.85mW 0.12mm2 1.0V 11位20 ms /s算法ADC, 65nm CMOS
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325946
J. Nam, Young-Deuk Jeon, Young‐Kyun Cho, Sang-Gug Lee, Jong-Kee Kwon
{"title":"A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS","authors":"J. Nam, Young-Deuk Jeon, Young‐Kyun Cho, Sang-Gug Lee, Jong-Kee Kwon","doi":"10.1109/ESSCIRC.2009.5325946","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325946","url":null,"abstract":"An 11-bit 20-MS/s algorithmic analog-to-digital converter (ADC) based on a dynamic biasing technique is proposed. A dynamic biasing technique is employed to an operational transconductance amplifier (OTA) for power reduction in sub-conversion stages. Besides, a distinct sampling clock scheme is taken to pre-amplifier for reducing aperture time errors. The prototype ADC is fabricated in a 65nm 1P6M CMOS process and features a maximum signal-to-noise-ratio and a spurious-free-dynamic-range of 60.4dB, and 69.2dB at Nyquist input frequency with 20MS/s from a 1.0V supply, respectively. About 22% of OTA power dissipation is reduced without performance degradation and totally 2.85mW is consumed.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"2673 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125414851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Merged power amplifier and mixer circuit topology for radar applications in CMOS CMOS中雷达应用的合并功率放大器和混频器电路拓扑
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325984
V. Issakov, M. Tiebout, H. Knapp, Yiqun Cao, W. Simbürger
{"title":"Merged power amplifier and mixer circuit topology for radar applications in CMOS","authors":"V. Issakov, M. Tiebout, H. Knapp, Yiqun Cao, W. Simbürger","doi":"10.1109/ESSCIRC.2009.5325984","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325984","url":null,"abstract":"This paper presents a circuit topology merging power amplifier and mixer functionalities in a single circuit. The amplified local oscillator signal in the transmitter path is used simultaneously for the mixing operation along with the received radio-frequency signal, applied to the output of the power amplifier. The transistors at the output stage of the power amplifier are used for both amplification and passive mixing. The conversion loss of the mixer can be minimized, whilst the performance of the power amplifier is not affected. This approach is verified in measurement of a merged power-amplifier-mixer circuit in 0.13 µm CMOS technology. The mixer path offers a conversion loss of 10 dB, whilst the power amplifier achieves on-board output power of 7 dBm. The presented concept can be particularly advantageous for compact integrated monostatic radar solutions for low-cost mass-market applications.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"119 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114133190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A digitally-assisted electrothermal frequency-locked loop 一个数字辅助电热锁频环路
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326001
S. M. Kashmiri, K. Makinwa
{"title":"A digitally-assisted electrothermal frequency-locked loop","authors":"S. M. Kashmiri, K. Makinwa","doi":"10.1109/ESSCIRC.2009.5326001","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326001","url":null,"abstract":"A digitally-assisted electrothermal frequency-locked loop (FLL) is presented, whose output frequency is determined by the temperature-dependent thermal diffusivity of bulk silicon. In contrast to previous work, its noise bandwidth is defined by a digital, rather than an analog, filter. This obviates the need for external capacitors, thus enabling full CMOS integration. Without trimming, an implementation in a 0.7µm CMOS process achieves an output frequency spread of about ±0.3% (3σ) from −55 °C to 125 °C. This corresponds to a temperature sensing inaccuracy of about ±0.7 °C (3σ).","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123746026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Area and latency optimized high-throughput Min-Sum based LDPC decoder architectures 面积和延迟优化的基于最小和的高吞吐量LDPC解码器架构
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325964
Matthias Korb, T. Noll
{"title":"Area and latency optimized high-throughput Min-Sum based LDPC decoder architectures","authors":"Matthias Korb, T. Noll","doi":"10.1109/ESSCIRC.2009.5325964","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325964","url":null,"abstract":"Low Density Parity Check codes (LDPC) achieve bit error rates close to the Shannon limit. Therefore, codes with large block lengths are required. These codes lead to high block latencies and especially to complex decoders, which are contrary to the demanded high throughput rates. Mainly two high throughput decoder architectures are known. A bit-parallel architecture yields in a small block latency and a high throughput rate while a bit-serial architecture features a small silicon area. We present a systematic search for high-throughput Min-Sum based LDPC decoder architectures leading to a set of AT-efficient architectures. In comparison to other decoder implementations accurate cost models predict a 60 % reduction in AT-complexity. Furthermore, the introduction of a digit-serial communication enables a trade-off between area and throughput rate retaining the low AT-complexity.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131224007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High precision optical angle measuring method applicable in standard CMOS technology 适用于标准CMOS技术的高精度光学角度测量方法
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325982
C. Koch, J. Oehm, Andreas Gornik
{"title":"High precision optical angle measuring method applicable in standard CMOS technology","authors":"C. Koch, J. Oehm, Andreas Gornik","doi":"10.1109/ESSCIRC.2009.5325982","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325982","url":null,"abstract":"In this paper a new concept for high precision angle measurement in standard CMOS technology is presented. In comparison to previous works, the complexness of the sensor topology is strongly reduced, the measuring range and the accuracy are significantly increased. The wavelength and the light intensity have a negligible influence on the accuracy of the sensor. In contrast to the previous concept, where SOI technology is mandatory, this new sensor concept can also be realised using standard CMOS technology.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133059237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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