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Wide-band variable-gain LNA in 65 nm CMOS with inverter based amplifier for multi-tuners cable TV reception 基于逆变器放大器的65纳米CMOS宽带可变增益LNA多调谐器有线电视接收
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325971
S. Robert, Olivier Abed-Meraim, Luca Lo Coco
{"title":"Wide-band variable-gain LNA in 65 nm CMOS with inverter based amplifier for multi-tuners cable TV reception","authors":"S. Robert, Olivier Abed-Meraim, Luca Lo Coco","doi":"10.1109/ESSCIRC.2009.5325971","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325971","url":null,"abstract":"This paper presents a wide band Low Noise Amplifier (LNA) intended for cable TV reception. The topology used for this amplifier differs from usual ones, and leads to a highly linear LNA. It was built in TSMC 65-nm CMOS technology. The measurements with 2.3 V supply voltage show 5.7 dB Noise Figure (NF), +64 dBmV IIP3, +80 dBmV IIP2 with 65 mW power consumption. The gain varies from 3 dB to 15 dB with 3 dB steps.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133868698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Improved on-chip components for integrated DC-DC converters in 0.13 µm CMOS 改进的片上元件，用于0.13µm CMOS集成DC-DC转换器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325987
Jinhua Ni, Zhiliang Hong, B. Liu
{"title":"Improved on-chip components for integrated DC-DC converters in 0.13 µm CMOS","authors":"Jinhua Ni, Zhiliang Hong, B. Liu","doi":"10.1109/ESSCIRC.2009.5325987","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325987","url":null,"abstract":"A fully-integrated DC-DC converter with on-chip inductors and capacitors is realized in a 0.13 µm CMOS technology. By using an asymmetric, high-Q inductor, power efficiency comparable to that of converters implemented with off-chip inductors is achieved. Straightforward analysis of high-density capacitor structure results in minimal ESR and optimal filtering of the output. The manufactured converter achieves a peak power efficiency of 80.5 % for an optimal load current of 170 mA and a voltage conversion ratio of 0.76 when switching at 180 MHz. This design is approximately 23 % more efficient than a linear regulator at a voltage conversion ratio of 0.55. A simple voltage mode PWM control keeps the output stable at the desired level, under load conditions from 0 mW to 720 mW.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"43 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123171529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Wideband inductorless minimal area RF front-end 宽带无电感最小面积射频前端
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326014
S. Hampel, O. Schmitz, M. Tiebout, I. Rolfes
{"title":"Wideband inductorless minimal area RF front-end","authors":"S. Hampel, O. Schmitz, M. Tiebout, I. Rolfes","doi":"10.1109/ESSCIRC.2009.5326014","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326014","url":null,"abstract":"This paper presents the design of a fully integrated inductorless wideband RF front-end for wireless applications including WLAN, Bluetooth and UWB. The core of the circuit is comprised of a two stage LNA, followed by a standard Gilbert cell mixer and an output buffer for measurement purposes. The chip was fabricated in 65nm standard CMOS process. The RX offers an input matching of better than −10 dB in a bandwidth from 2.1 GHz to 8.2 GHz. To compensate the gain roll off the LNA incorporates an active inductor load, leading to a peak conversion gain of 20 dB at 3.5 GHz with a 3-dB bandwidth covering the whole matching frequency range. The minimal noise figure is 5.85 dB and kept below 7.5 dB within the whole matching and gain bandwidth. The linearity in terms of P1dB,out and oIP3 offers nearly constant behavior with −2 dBm and 7 dBm respectively. Excluding the buffer the circuit dissipates 47 mW. The die size of 370 µm by 570 µm is mainly dominated by the pad-frame, while the active area takes up only 0.05 mm2.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122998003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 20-GHz 1-V VCO with dual-transformer configuration and a pseudo-static divider on self-stabilized concept 基于自稳定概念的20 ghz 1 v双变压器压控振荡器和伪静态分压器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325973
Takahiro Nakamura, T. Masuda, N. Shiramizu, A. Nakamura, K. Washio
{"title":"A 20-GHz 1-V VCO with dual-transformer configuration and a pseudo-static divider on self-stabilized concept","authors":"Takahiro Nakamura, T. Masuda, N. Shiramizu, A. Nakamura, K. Washio","doi":"10.1109/ESSCIRC.2009.5325973","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325973","url":null,"abstract":"A 20-GHz 1-V VCO with dual-transformer configuration and a self-stabilized pseudo-static frequency divider were developed using 0.18-µm SiGe BiCMOS technology. For the VCO, a combination of two types of transformers, which exhibit high-input impedance and capacitive-input impedance, contributes to the output of two sets of differential signals for mixers and the divider, maintaining both a wide frequency-tuning range and low-phase noise. The measured phase noise of the VCO at a 1-MHz offset frequency is −115 dBc/Hz with dissipating 7.5-mW DC power. The Figure of merit of the VCO is −197 dB, which is the best value among 20-GHz-class Si-based VCOs to our best knowledge. For the divider, a two-stage block configuration consisting of an inverter, a mixer, and a low-pass filter (LPF) contributes to enhancing the operation frequency range. The divider is designed to have high conversion gain at low frequency and small circuit delay at high frequency for wide operation range. The measured operation frequency of the divider is from 7 to 26 GHz while dissipating only 1.15-mW DC power and occupying small area of 0.004 mm2. These excellent results indicate that the proposed techniques are very suitable for lowpower transceivers of quasi-millimeter-wave wireless communication systems.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123880754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 11.5-Gbps LDPC decoder based on CP-PEG code construction 基于CP-PEG编码结构的11.5 gbps LDPC解码器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325933
Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, W. Fang, Chen-Yi Lee
{"title":"A 11.5-Gbps LDPC decoder based on CP-PEG code construction","authors":"Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, W. Fang, Chen-Yi Lee","doi":"10.1109/ESSCIRC.2009.5325933","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325933","url":null,"abstract":"In this paper, a LDPC decoder chip based on CPPEG code construction is presented. The (2048, 1920) irregular LDPC code generated by CP-PEG algorithm has better performance than other PEG-based codes; however, the large check node degrees introduced by high code-rate 15/16 become the implementation bottleneck. To design such a high coderate LDPC decoder, our approach features variable-node-centric sequential scheduling to reduce iteration number, single piplelined decoder architecture to lessen the message storage memory size, as well as optimized check node unit to further compress the register number. Overall 73% message storage memory is saved as compared with traditional architecture. Fabricated in 90nm 1P9M CMOS technology, a test deocder chip could achieve maximum 11.5 Gbps throughput under 1.4V supply voltage with core area of 2.7 × 1.4 mm2. The energy efficiency is only 0.033 nJ/bit with 5.77 Gbps at 0.8V to meet IEEE 802.15.3c requirements.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131468966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A low variation GHz ring oscillator with addition-based current source 一种带有附加型电流源的低变化GHz环形振荡器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325968
Xuan Zhang, A. Apsel
{"title":"A low variation GHz ring oscillator with addition-based current source","authors":"Xuan Zhang, A. Apsel","doi":"10.1109/ESSCIRC.2009.5325968","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325968","url":null,"abstract":"A 3-stage current-starved ring oscillator with 65.1% reduction in process variation in a 90nm CMOS process is presented. The low variation is achieved without degrading the mean operating frequency through the implementation of an addition-based current source to replace a single transistor current source in each inverter stage. No post-fabrication trimming or calibration is required. Circuit simulations indicate that the proposed circuitry is well suited for scaling beyond 90nm. Measurements that are taken from 2 separate wafers and 167 test chips show 65.1% less process variation in output frequency, compared to a conventional current-starved ring oscillator. The power overhead for the additional circuitry is 33µW.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128712889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 300Hz 19b DR capacitive accelerometer based on a versatile front end in a 5th-order ΔΣ loop 一种300Hz 19b DR电容式加速度计，基于五阶ΔΣ回路的多功能前端
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326033
M. Pastre, M. Kayal, H. Schmid, A. Huber, P. Zwahlen, A. Nguyen, Yufeng Dong
{"title":"A 300Hz 19b DR capacitive accelerometer based on a versatile front end in a 5th-order ΔΣ loop","authors":"M. Pastre, M. Kayal, H. Schmid, A. Huber, P. Zwahlen, A. Nguyen, Yufeng Dong","doi":"10.1109/ESSCIRC.2009.5326033","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326033","url":null,"abstract":"This paper presents a 5<sup>th</sup>-order ΔΣ capacitive accelerometer. The ΔΣ loop is implemented in mixed signal, the global 5<sup>th</sup>-order filter having a 2<sup>nd</sup>-order analog and a 3<sup>rd</sup>-order digital part. The system can be used with a wide range of sensors, because the mixed-signal front end is programmable. The ASIC developed comprises a voltage-mode preamplifier, two parallel demodulators implementing CDS, and a 7-bit Flash ADC. The latter drives a 3<sup>rd</sup>-order digital filter, which can be configured for different sensor parameters in order to ensure overall loop stability and optimize the noise performance. With a low-noise MEMS sensor, the system achieves a 19-bit DR and a 16-bit SNR, both over a 300Hz bandwidth.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121098033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
A multifunction low-power preamplifier for MEMS capacitive microphones 一种用于MEMS电容式传声器的多功能低功率前置放大器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325947
S. A. Jawed, J. Nielsen, M. Gottardi, A. Baschirotto, E. Bruun
{"title":"A multifunction low-power preamplifier for MEMS capacitive microphones","authors":"S. A. Jawed, J. Nielsen, M. Gottardi, A. Baschirotto, E. Bruun","doi":"10.1109/ESSCIRC.2009.5325947","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325947","url":null,"abstract":"A multi-function two-stage chopper-stabilized preamplifier (PAMP) for MEMS capacitive microphones (MCM) is presented. The PAMP integrates digitally controllable gain, high-pass filtering and offset control, adding flexibility to the front-end readout of MCMs. The first stage of the PAMP consists of a source-follower (SF) while the second-stage is a capacitive gain stage. The second-stage employs chopper-stabilization (CHS), while SF buffer shields the MCM sensor from the switching spurs. The PAMP uses MW poly bias resistors for the second-stage, exploiting Miller effect to achieve flat audio-band response. The gain and high-pass filtering corner can be adjusted by digitally controlling the capacitor banks in the PAMP. The offset-control feature of the PAMP is implemented using a narrow-band low-pass gm-C filter. The PAMP occupies 950µm × 950µm in 0.35µm CMOS technology and draws a 50µA total current from a 1.8V single supply. The PAMP achieves SNDR of 44dBA/Pa (elec. meas.) and 27dBA/Pa (acoustic meas.) and a conversion range from 50dBSPL to 120dBSPL.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127172012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
An 11.1Gbps analog PRML receiver for EDC of up to 400km-reach WDM fiber-optic links 11.1Gbps模拟PRML接收器，用于高达400km的WDM光纤链路的EDC
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326025
S. Elahmadi, M. Bussmann, Jomo Edwards, K. Tran, L. Linder, Christopher Gill, Harry Tan, D. Ng, D. Baranauskas, D. Zelenin
{"title":"An 11.1Gbps analog PRML receiver for EDC of up to 400km-reach WDM fiber-optic links","authors":"S. Elahmadi, M. Bussmann, Jomo Edwards, K. Tran, L. Linder, Christopher Gill, Harry Tan, D. Ng, D. Baranauskas, D. Zelenin","doi":"10.1109/ESSCIRC.2009.5326025","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326025","url":null,"abstract":"A dispersion tolerant receiver for fiber-optic links, in 0.18µm SiGe BiCMOS, implements a Class-2 Partial Response Maximum Likelihood (PRML) equalization entirely in the analog domain. Post-FEC error free operation is achieved with data received from over 400km of uncompensated single mode fiber (SMF). The receiver complies with XFI Jitter specifications for Telecom (SONET OC-192 and G.709 “OTU-2”).","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126433524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior 基于45nm CMOS的0.45pJ/ convstep 1.2Gs/s 6b全nyquist非校准闪存ADC及其缩放行为
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326002
Paul Veldhorst, G. Goksun, A. Annema, B. Nauta, B. Buter, M. Vertregt
{"title":"A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior","authors":"Paul Veldhorst, G. Goksun, A. Annema, B. Nauta, B. Buter, M. Vertregt","doi":"10.1109/ESSCIRC.2009.5326002","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326002","url":null,"abstract":"A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties; a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121386072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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