Paul Veldhorst, G. Goksun, A. Annema, B. Nauta, B. Buter, M. Vertregt
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引用次数: 10
摘要
提出了一种采用标准45nm CMOS工艺的6位1.2 g /s非校准闪存ADC，在全奈奎斯特带宽下可实现0.45pJ/ convstep。通过对放大器模块的全面优化，以及比较器和编码阶段的创新，实现了高效节能的操作。非校准闪存ADC的性能与器件性能直接相关;我们的ADC在CMOS技术内和跨CMOS技术的缩放分析，让我们深入了解45纳米技术在AD转换器设计中的出色可用性。
A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior
A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties; a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design.
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