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A 400-MHz CMOS radio front-end for ultra low-power medical implantable applications 一个400-MHz CMOS无线电前端超低功耗医疗植入式应用
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325972
F. Carrara, A. Italia, G. Palmisano, R. Guerra
{"title":"A 400-MHz CMOS radio front-end for ultra low-power medical implantable applications","authors":"F. Carrara, A. Italia, G. Palmisano, R. Guerra","doi":"10.1109/ESSCIRC.2009.5325972","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325972","url":null,"abstract":"A 400-MHz ultra low-power radio front-end for medical implantable applications has been implemented in a 0.13-µm CMOS technology. The circuit consists of an up-converter, a down-converter, and a LO frequency synthesizer. The up-converter employs a push-pull PA, which achieves a saturated output power of 0 dBm with a maximum power added efficiency of 32%. Moreover, the up-converter exhibits a −30-dBc ACPR at an output power of −0.5 dBm with a 200 kbit/s GFSK input signal. The down-converter provides excellent linearity performance exhibiting an output compression point of 1.13 Vpp, an IIP3 of −23 dBm, and an IIP2 of 8.7 dBm despite a current consumption as low as 1.5 mA. It has a 45-dB conversion gain and a 7.4-dB noise figure. The LO frequency synthesizer features a fully-integrated LC VCO and programmable channel steps. It provides a phase noise better than −96 dBc/Hz at 100-kHz offset and a spur rejection of −52 dBc. Operating from a 1.2-V supply, the overall front-end draws 3 mA in receive mode and 4.5 mA in transmit mode.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127937333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 60GHz power amplifier with 14.5dBm saturation power and 25% peak PAE in CMOS 65nm SOI 60GHz功率放大器，饱和功率14.5dBm，峰值PAE为25%，采用CMOS 65nm SOI
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326013
A. Siligaris, Y. Hamada, C. Mounet, C. Raynaud, B. Martineau, N. Deparis, N. Rolland, M. Fukaishi, P. Vincent
{"title":"A 60GHz power amplifier with 14.5dBm saturation power and 25% peak PAE in CMOS 65nm SOI","authors":"A. Siligaris, Y. Hamada, C. Mounet, C. Raynaud, B. Martineau, N. Deparis, N. Rolland, M. Fukaishi, P. Vincent","doi":"10.1109/ESSCIRC.2009.5326013","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326013","url":null,"abstract":"A 60GHz wideband power amplifier (PA) is fabricated in standard CMOS SOI 65nm process. The PA is constituted by two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high resistivity SOI substrate. The PA measurements are carried out for supply voltages VDD going from 1.2V to 2.6V and achieve a saturation power of 10dBm to 16.5dBm respectively. The peak power added efficiency is higher than 20% for all applied VDD values.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127657798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A low power, area efficient limiting amplifier in 90nm CMOS 一种低功耗、面积高效的90nm CMOS限幅放大器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325997
F. Tavernier, M. Steyaert
{"title":"A low power, area efficient limiting amplifier in 90nm CMOS","authors":"F. Tavernier, M. Steyaert","doi":"10.1109/ESSCIRC.2009.5325997","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325997","url":null,"abstract":"A low power limiting amplifier with area efficient offset compensation in 90nm CMOS is presented. The large time constant needed in the offset compensation feedback loop is boosted by an inverting amplifier to reduce the chip area. On top of this, to reduce the chip area even more, negative capacitors are applied to increase the bandwidth instead of making use of the inductive peaking technique. The proposed circuit has a small-signal gain of 35dB and a bandwidth of 4.15GHz. The input sensitivity for a BER of 10−12 is 2.75mV, 2.9mV and 3.75mV for a bitrate of 3, 4 and 5Gbit/s respectively. The power consumption is only 14.7mW and the area of the circuit is 0.12mm2.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127679009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Low-jitter fractional spread-spectrum clock generator using fast-settling dual charge-pump technique for Serial-ATA application 采用快速沉降双电荷泵技术的串行ata低抖动分数阶扩频时钟发生器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326000
T. Kawamoto, Tomoaki Takahashi, Shigeyuki Suzuki, T. Noto, K. Asahina
{"title":"Low-jitter fractional spread-spectrum clock generator using fast-settling dual charge-pump technique for Serial-ATA application","authors":"T. Kawamoto, Tomoaki Takahashi, Shigeyuki Suzuki, T. Noto, K. Asahina","doi":"10.1109/ESSCIRC.2009.5326000","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326000","url":null,"abstract":"A low-jitter fractional spread-spectrum clock generator (SSCG) by utilizing a fast-settling dual charge-pump (CP) technique has been developed for Serial-ATA (SATA) applications. The proposed fast-settling dual CP technique not only reduced a design area but also shortened settling-time by controlling the CP operation sequence in an SSCG settling period. A multi-modulus divider using differential dynamic flip-flops was applied to our SSCG to reduce the design area, power consumption, and jitter. The proposed SSCG for SATA generation I was fabricated in a 0.13 µm CMOS process. The settling-time was 3.91 µs faster than that of a conventional SSCG, 8.11 µs. The random jitter and total jitter in 250 cycles at 1.5 GHz were 2.7 psrms and 3.3 psrms, respectively. The EMI reduction that meets SATA specification was 10.0 dB. The design area and the power consumption were 300 x 700 µm2 and 18 mW, respectively.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127724093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 118.4GB/s multi-casting network-on-chip for real-time object recognition processor 一个118.4GB/s的多播片上网络实时目标识别处理器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325978
Joo-Young Kim, Kwanho Kim, Seungjin Lee, Minsu Kim, Jinwook Oh, H. Yoo
{"title":"A 118.4GB/s multi-casting network-on-chip for real-time object recognition processor","authors":"Joo-Young Kim, Kwanho Kim, Seungjin Lee, Minsu Kim, Jinwook Oh, H. Yoo","doi":"10.1109/ESSCIRC.2009.5325978","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325978","url":null,"abstract":"A 118.4GB/s multi-casting network-on-chip (MC-NoC) is developed as communication platform for a real-time object recognition processor. To support application-specific data transactions, the MC-NoC adopts the combination of hierarchical star and ring topology with the multi-casting capability. As a result, the proposed MC-NoC improves data transaction time and energy consumption by 20% and 23%, respectively, under target object recognition traffic. The 350k gates MC-NoC, fabricated in a 0.13µm CMOS process, consumes 48mW at 400MHz, 1.2V.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129202720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low-power wide-band digital frequency synthesizer for cognitive radio sensor units 一种用于认知无线电传感器单元的低功耗宽带数字频率合成器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325967
Liangge Xu, K. Stadius, J. Ryynänen
{"title":"A low-power wide-band digital frequency synthesizer for cognitive radio sensor units","authors":"Liangge Xu, K. Stadius, J. Ryynänen","doi":"10.1109/ESSCIRC.2009.5325967","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325967","url":null,"abstract":"This paper presents the design of a wide-band digital frequency synthesizer for cognitive radio sensor units. It is based on an all-digital phase-locked loop, and employs a digitally controlled ring oscillator with an LC tank introduced to extend tuning range and reduce power dissipation. Adaptive frequency calibration based on binary search is used for fast frequency settling. Fabricated in a 65-nm CMOS, the frequency synthesizer has an active area of 0.3 mm2 and achieves a frequency tuning range of 2.7 to 6.1 GHz, with power consumption less than 22 mW from a 1.2-V supply. Measured phase noise at 6-GHz frequency is −92 dBc/Hz at 1-MHz offset.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128732781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
100–1000 MHz cutoff frequency, 0–12 dB boost programmable Gm-C filter with digital calibration for HDD read channel 100-1000 MHz截止频率，0-12 dB升压可编程Gm-C滤波器，用于硬盘读取通道的数字校准
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326022
T. Terada, T. Yamawaki, M. Kokubo, Koji Nasu
{"title":"100–1000 MHz cutoff frequency, 0–12 dB boost programmable Gm-C filter with digital calibration for HDD read channel","authors":"T. Terada, T. Yamawaki, M. Kokubo, Koji Nasu","doi":"10.1109/ESSCIRC.2009.5326022","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326022","url":null,"abstract":"A programmable Gm-C filter with digital calibration for hard disk drive read channels was developed. The filter has gm and boost tuning circuits and DC offset cancellation circuits. Moreover, it has two types of digital calibrations for achieving a robust filter response. One is an initial calibration to compensate for the filter response variations over process changes. The other is a periodic calibration to compensate for the variations over supply voltage and temperature changes. The periodic calibration operates in the duration between the servo and the data operation modes in the read channel. As a result, the filter response is robust over process, supply voltage, and temperature variations. The programmable range of the cutoff frequency and the boost are 100-1000 MHz and 0-12 dB, respectively.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115451407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 2.4-GHz 24-dBm SOI CMOS power amplifier with on-chip tunable matching network for enhanced efficiency in back-off 一种2.4 ghz 24dbm SOI CMOS功率放大器，具有片上可调谐匹配网络，可提高回退效率
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325995
F. Carrara, C. Presti, G. Palmisano
{"title":"A 2.4-GHz 24-dBm SOI CMOS power amplifier with on-chip tunable matching network for enhanced efficiency in back-off","authors":"F. Carrara, C. Presti, G. Palmisano","doi":"10.1109/ESSCIRC.2009.5325995","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325995","url":null,"abstract":"In this work, the potential of load adaptation for enhanced back-off efficiency in RF power amplifiers (PAs) is investigated through a 0.13-µm silicon-on-insulator (SOI) CMOS fabrication technology. To this aim, the first CMOS PA with fully integrated reconfigurable output matching network is presented. The PA delivers a 24-dBm maximum output power while operating at 2.4 GHz and 2-V supply voltage. A significant efficiency improvement of up to 34% is achieved through load adaptation, peak efficiency being as high as 65%. Linear operation is also demonstrated under two-tone excitation, since a 16-dBm output power is attained while complying with a −40-dBc IM3 specification.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115695356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS 单比特6.8mW 10MHz功率优化连续时间ΔΣ，在90nm CMOS中具有67dB DR
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326032
P. Crombez, G. V. D. Plas, M. Steyaert, J. Craninckx
{"title":"A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS","authors":"P. Crombez, G. V. D. Plas, M. Steyaert, J. Craninckx","doi":"10.1109/ESSCIRC.2009.5326032","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326032","url":null,"abstract":"High data rates and increased digitization require A/D converters with high dynamic range and bandwidth. In combination with low power consumption they are key for broadband wireless systems. A single bit continuous-time ΔΣ modulator with 10MHz signal bandwidth avoiding high speed DEM circuits in 1.2V 90nm digital CMOS is presented. It achieves an SNDR of 65dB while consuming only 6.8mW of power thanks to a global optimization at both architectural and circuit level. An overall energy efficiency of 0.24 pJ/conv is obtained by employing linearity enhanced integrators, a threshold configurable comparator enabling perfect loop delay compensation and low sensitive DAC integration.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115873112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An integrated 10A, 2.2ns rise-time laser-diode driver for LIDAR applications 用于激光雷达应用的集成10A, 2.2ns上升时间激光二极管驱动器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326005
M. Wens, Jean-Michel Redouté, Tim Blanchaert, Nicolas Bleyaert, M. Steyaert
{"title":"An integrated 10A, 2.2ns rise-time laser-diode driver for LIDAR applications","authors":"M. Wens, Jean-Michel Redouté, Tim Blanchaert, Nicolas Bleyaert, M. Steyaert","doi":"10.1109/ESSCIRC.2009.5326005","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326005","url":null,"abstract":"An integrated laser-diode driver for LIDAR applications in a 0.35 µm 80V CMOS technology is realized. The integration of the power switch as a n-DMOS allows a peak current of 10 A, with a corresponding rise-time of 2.2 ns and a fall-time of 2.4 ns. Up to the authors knowledge this is a first-time achievement on a monolithic die. The laser can be operated at a maximum duty-cycle of 0.1 %, with a pulse duration of 10 – 50 ns. To overcome the parasitic inductances and their associated voltage drop, a high voltage of 70 V is applied to the LIDAR circuit. In order to drive the power switch within its safe operating area and to make sure the rise- and fall-time is minimized, a pre-driver is integrated on the same die.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127221013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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