A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS

Abstract

High data rates and increased digitization require A/D converters with high dynamic range and bandwidth. In combination with low power consumption they are key for broadband wireless systems. A single bit continuous-time ΔΣ modulator with 10MHz signal bandwidth avoiding high speed DEM circuits in 1.2V 90nm digital CMOS is presented. It achieves an SNDR of 65dB while consuming only 6.8mW of power thanks to a global optimization at both architectural and circuit level. An overall energy efficiency of 0.24 pJ/conv is obtained by employing linearity enhanced integrators, a threshold configurable comparator enabling perfect loop delay compensation and low sensitive DAC integration.