A 60GHz power amplifier with 14.5dBm saturation power and 25% peak PAE in CMOS 65nm SOI

2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI:10.1109/ESSCIRC.2009.5326013

A. Siligaris, Y. Hamada, C. Mounet, C. Raynaud, B. Martineau, N. Deparis, N. Rolland, M. Fukaishi, P. Vincent

引用次数: 24

Abstract

A 60GHz wideband power amplifier (PA) is fabricated in standard CMOS SOI 65nm process. The PA is constituted by two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high resistivity SOI substrate. The PA measurements are carried out for supply voltages VDD going from 1.2V to 2.6V and achieve a saturation power of 10dBm to 16.5dBm respectively. The peak power added efficiency is higher than 20% for all applied VDD values.

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60GHz功率放大器，饱和功率14.5dBm，峰值PAE为25%，采用CMOS 65nm SOI

采用标准CMOS SOI 65nm工艺制备了60GHz宽带功率放大器(PA)。PA由两个级联代码阶段组成。输入、输出和级间匹配使用共面波导(CPW)传输线，由于SOI衬底具有高电阻率，因此损耗低。在电源电压VDD从1.2V到2.6V范围内进行了PA测量，饱和功率分别为10dBm到16.5dBm。对于所有应用的VDD值，峰值功率增加效率高于20%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2009 Proceedings of ESSCIRC

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