A 2.4-GHz 24-dBm SOI CMOS power amplifier with on-chip tunable matching network for enhanced efficiency in back-off

F. Carrara, C. Presti, G. Palmisano
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引用次数: 3

Abstract

In this work, the potential of load adaptation for enhanced back-off efficiency in RF power amplifiers (PAs) is investigated through a 0.13-µm silicon-on-insulator (SOI) CMOS fabrication technology. To this aim, the first CMOS PA with fully integrated reconfigurable output matching network is presented. The PA delivers a 24-dBm maximum output power while operating at 2.4 GHz and 2-V supply voltage. A significant efficiency improvement of up to 34% is achieved through load adaptation, peak efficiency being as high as 65%. Linear operation is also demonstrated under two-tone excitation, since a 16-dBm output power is attained while complying with a −40-dBc IM3 specification.
一种2.4 ghz 24dbm SOI CMOS功率放大器,具有片上可调谐匹配网络,可提高回退效率
在这项工作中,通过0.13 μ m绝缘体上硅(SOI) CMOS制造技术,研究了射频功率放大器(PAs)中负载自适应增强退退效率的潜力。为此,提出了第一个具有完全集成的可重构输出匹配网络的CMOS PA。在2.4 GHz和2v供电电压下,PA可提供24dbm的最大输出功率。通过负载适应,效率显著提高了34%,峰值效率高达65%。在双音激励下也演示了线性操作,因为在符合- 40 dbc IM3规范的同时获得了16 dbm的输出功率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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