{"title":"A 400-MHz CMOS radio front-end for ultra low-power medical implantable applications","authors":"F. Carrara, A. Italia, G. Palmisano, R. Guerra","doi":"10.1109/ESSCIRC.2009.5325972","DOIUrl":null,"url":null,"abstract":"A 400-MHz ultra low-power radio front-end for medical implantable applications has been implemented in a 0.13-µm CMOS technology. The circuit consists of an up-converter, a down-converter, and a LO frequency synthesizer. The up-converter employs a push-pull PA, which achieves a saturated output power of 0 dBm with a maximum power added efficiency of 32%. Moreover, the up-converter exhibits a −30-dBc ACPR at an output power of −0.5 dBm with a 200 kbit/s GFSK input signal. The down-converter provides excellent linearity performance exhibiting an output compression point of 1.13 Vpp, an IIP3 of −23 dBm, and an IIP2 of 8.7 dBm despite a current consumption as low as 1.5 mA. It has a 45-dB conversion gain and a 7.4-dB noise figure. The LO frequency synthesizer features a fully-integrated LC VCO and programmable channel steps. It provides a phase noise better than −96 dBc/Hz at 100-kHz offset and a spur rejection of −52 dBc. Operating from a 1.2-V supply, the overall front-end draws 3 mA in receive mode and 4.5 mA in transmit mode.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Proceedings of ESSCIRC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2009.5325972","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
A 400-MHz ultra low-power radio front-end for medical implantable applications has been implemented in a 0.13-µm CMOS technology. The circuit consists of an up-converter, a down-converter, and a LO frequency synthesizer. The up-converter employs a push-pull PA, which achieves a saturated output power of 0 dBm with a maximum power added efficiency of 32%. Moreover, the up-converter exhibits a −30-dBc ACPR at an output power of −0.5 dBm with a 200 kbit/s GFSK input signal. The down-converter provides excellent linearity performance exhibiting an output compression point of 1.13 Vpp, an IIP3 of −23 dBm, and an IIP2 of 8.7 dBm despite a current consumption as low as 1.5 mA. It has a 45-dB conversion gain and a 7.4-dB noise figure. The LO frequency synthesizer features a fully-integrated LC VCO and programmable channel steps. It provides a phase noise better than −96 dBc/Hz at 100-kHz offset and a spur rejection of −52 dBc. Operating from a 1.2-V supply, the overall front-end draws 3 mA in receive mode and 4.5 mA in transmit mode.