J. Nam, Young-Deuk Jeon, Young‐Kyun Cho, Sang-Gug Lee, Jong-Kee Kwon
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引用次数: 3
摘要
提出了一种基于动态偏置技术的11位20 ms /s算法模数转换器(ADC)。采用动态偏置技术来降低跨导运算放大器的子转换级功率。此外，前置放大器采用了不同的采样时钟方案，减小了孔径时间误差。该原型ADC采用65nm 1P6M CMOS工艺制造，在1.0V电源、20MS/s的Nyquist输入频率下，最大信噪比和无杂散动态范围分别为60.4dB和692 db。在不降低性能的情况下，OTA功耗降低了约22%，总共消耗了2.85mW。
A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS
An 11-bit 20-MS/s algorithmic analog-to-digital converter (ADC) based on a dynamic biasing technique is proposed. A dynamic biasing technique is employed to an operational transconductance amplifier (OTA) for power reduction in sub-conversion stages. Besides, a distinct sampling clock scheme is taken to pre-amplifier for reducing aperture time errors. The prototype ADC is fabricated in a 65nm 1P6M CMOS process and features a maximum signal-to-noise-ratio and a spurious-free-dynamic-range of 60.4dB, and 69.2dB at Nyquist input frequency with 20MS/s from a 1.0V supply, respectively. About 22% of OTA power dissipation is reduced without performance degradation and totally 2.85mW is consumed.
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