Area and latency optimized high-throughput Min-Sum based LDPC decoder architectures

Abstract

Low Density Parity Check codes (LDPC) achieve bit error rates close to the Shannon limit. Therefore, codes with large block lengths are required. These codes lead to high block latencies and especially to complex decoders, which are contrary to the demanded high throughput rates. Mainly two high throughput decoder architectures are known. A bit-parallel architecture yields in a small block latency and a high throughput rate while a bit-serial architecture features a small silicon area. We present a systematic search for high-throughput Min-Sum based LDPC decoder architectures leading to a set of AT-efficient architectures. In comparison to other decoder implementations accurate cost models predict a 60 % reduction in AT-complexity. Furthermore, the introduction of a digit-serial communication enables a trade-off between area and throughput rate retaining the low AT-complexity.