基于半积分次谐波锁定的0.18µm CMOS低相位噪声注入锁相差动环压控振荡器

Yuka Kobayashi, S. Amakawa, N. Ishihara, K. Masu
{"title":"基于半积分次谐波锁定的0.18µm CMOS低相位噪声注入锁相差动环压控振荡器","authors":"Yuka Kobayashi, S. Amakawa, N. Ishihara, K. Masu","doi":"10.1109/ESSCIRC.2009.5325965","DOIUrl":null,"url":null,"abstract":"Design and implementation of a CMOS differential ring-VCO that locks at half-integral (1.5, 2.5, 3.5, ⋯) as well as integral (1, 2, 3, ⋯) multiples of the injected reference frequency fref are presented. The advantage of half-integral subharmonic locking is that, for a given VCO output frequency step, the output phase noise can be lowered than when using integral subharmonic locking because of the higher (2x) reference frequency. For example, the 1-MHz-offset phase noise at a VCO output frequency of 1.5GHz was −136 dBc/Hz when locked to an integral subharmonic of fref = 0.5 GHz, whereas it was as low as −139 dBc/Hz when locked to a half-integral subharmonic of fref = 1.0 GHz. The ring-VCO was fabricated with a 0.18µm CMOS process. An explanation is given as to why it locks to half-integral subharmonics and how such an oscillator could be designed. Half-integral or, more generally, nonintegral subharmonic locking could make an effective means to reduce the phase noise of high-resolution injection-locked VCOs.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"A low-phase-noise injection-locked differential ring-VCO with half-integral subharmonic locking in 0.18 µm CMOS\",\"authors\":\"Yuka Kobayashi, S. Amakawa, N. Ishihara, K. Masu\",\"doi\":\"10.1109/ESSCIRC.2009.5325965\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Design and implementation of a CMOS differential ring-VCO that locks at half-integral (1.5, 2.5, 3.5, ⋯) as well as integral (1, 2, 3, ⋯) multiples of the injected reference frequency fref are presented. The advantage of half-integral subharmonic locking is that, for a given VCO output frequency step, the output phase noise can be lowered than when using integral subharmonic locking because of the higher (2x) reference frequency. For example, the 1-MHz-offset phase noise at a VCO output frequency of 1.5GHz was −136 dBc/Hz when locked to an integral subharmonic of fref = 0.5 GHz, whereas it was as low as −139 dBc/Hz when locked to a half-integral subharmonic of fref = 1.0 GHz. The ring-VCO was fabricated with a 0.18µm CMOS process. An explanation is given as to why it locks to half-integral subharmonics and how such an oscillator could be designed. Half-integral or, more generally, nonintegral subharmonic locking could make an effective means to reduce the phase noise of high-resolution injection-locked VCOs.\",\"PeriodicalId\":258889,\"journal\":{\"name\":\"2009 Proceedings of ESSCIRC\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Proceedings of ESSCIRC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2009.5325965\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Proceedings of ESSCIRC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2009.5325965","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20

摘要

提出了一种锁定在注入参考频率的半积分(1.5、2.5、3.5,⋯)和积分(1、2、3,⋯)倍的CMOS差分环压控振荡器的设计和实现。半积分次谐波锁定的优点是,对于给定的VCO输出频率步长,由于参考频率更高(2x),因此输出相位噪声可以比使用积分次谐波锁定时降低。例如,在VCO输出频率为1.5GHz时,当锁定到fref = 0.5 GHz的积分次谐波时,1 mhz偏置相位噪声为- 136 dBc/Hz,而当锁定到fref = 1.0 GHz的半积分次谐波时,其相位噪声低至- 139 dBc/Hz。环形压控振荡器采用0.18µm CMOS工艺制备。给出了一个解释,为什么它锁定到半积分次谐波,以及如何设计这样一个振荡器。半积分或更一般地说,非积分次谐波锁相可以成为降低高分辨率注入锁相振荡器相位噪声的有效手段。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A low-phase-noise injection-locked differential ring-VCO with half-integral subharmonic locking in 0.18 µm CMOS
Design and implementation of a CMOS differential ring-VCO that locks at half-integral (1.5, 2.5, 3.5, ⋯) as well as integral (1, 2, 3, ⋯) multiples of the injected reference frequency fref are presented. The advantage of half-integral subharmonic locking is that, for a given VCO output frequency step, the output phase noise can be lowered than when using integral subharmonic locking because of the higher (2x) reference frequency. For example, the 1-MHz-offset phase noise at a VCO output frequency of 1.5GHz was −136 dBc/Hz when locked to an integral subharmonic of fref = 0.5 GHz, whereas it was as low as −139 dBc/Hz when locked to a half-integral subharmonic of fref = 1.0 GHz. The ring-VCO was fabricated with a 0.18µm CMOS process. An explanation is given as to why it locks to half-integral subharmonics and how such an oscillator could be designed. Half-integral or, more generally, nonintegral subharmonic locking could make an effective means to reduce the phase noise of high-resolution injection-locked VCOs.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信