{"title":"8阶MASH δ - σ， OSR为3","authors":"T. Caldwell, D. Johns","doi":"10.1109/ESSCIRC.2009.5325962","DOIUrl":null,"url":null,"abstract":"This paper demonstrates that a high-order MASH delta-sigma modulator with a very low oversampling ratio can attain performance similar to a pipelined converter. The delta-sigma architecture fabricated is an 8-stage cascade of 1st-order stages with an oversampling ratio of 3 and realized in a 0.18µm CMOS process. The modulator attains an SNDR of 60 dB at a 50MHz sampling frequency and an 8.33MHz input bandwidth.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"An 8th-order MASH delta-sigma with an OSR of 3\",\"authors\":\"T. Caldwell, D. Johns\",\"doi\":\"10.1109/ESSCIRC.2009.5325962\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper demonstrates that a high-order MASH delta-sigma modulator with a very low oversampling ratio can attain performance similar to a pipelined converter. The delta-sigma architecture fabricated is an 8-stage cascade of 1st-order stages with an oversampling ratio of 3 and realized in a 0.18µm CMOS process. The modulator attains an SNDR of 60 dB at a 50MHz sampling frequency and an 8.33MHz input bandwidth.\",\"PeriodicalId\":258889,\"journal\":{\"name\":\"2009 Proceedings of ESSCIRC\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Proceedings of ESSCIRC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2009.5325962\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Proceedings of ESSCIRC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2009.5325962","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper demonstrates that a high-order MASH delta-sigma modulator with a very low oversampling ratio can attain performance similar to a pipelined converter. The delta-sigma architecture fabricated is an 8-stage cascade of 1st-order stages with an oversampling ratio of 3 and realized in a 0.18µm CMOS process. The modulator attains an SNDR of 60 dB at a 50MHz sampling frequency and an 8.33MHz input bandwidth.
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