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Embedded analog-to-digital converters 嵌入式模数转换器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325932
K. Bult
{"title":"Embedded analog-to-digital converters","authors":"K. Bult","doi":"10.1109/ESSCIRC.2009.5325932","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325932","url":null,"abstract":"Systems-on-Chips (SoCs) have become a reality in the past decade. Several dozens of different functional blocks are being integrated on a single die, reaching transistor counts of up to half a billion. From the Analog portion of an SoC the Data Converters are probably among the most challenging blocks, often limiting system performance and dominating power dissipation. However, requirements regarding yield, die-size, scalability, noise immunity, power and the fact that logic is almost for free, cause distinct differences between embedded Data Converters and their stand-alone, usually general purpose, counterparts. This paper describes these differences and provides an overview of the state-of-the art in Analog-to-Digital Conversion.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129137990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit 一个1.69 Gb/s的区域效率AES加密核心与紧凑的即时密钥扩展单元
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326020
Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee
{"title":"A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit","authors":"Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/ESSCIRC.2009.5326020","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326020","url":null,"abstract":"The AES algorithm published in 2001 is now the most popular symmetric encryption algorithm. Several implementations have beed proposed but few of them considered the hardware cost and the throughput as a whole. This paper presents an AES core to be capable of both encryption and decryption with three different key lengths: 128-, 192-, and 256-bit. The overall hardware cost was optimized by a very compact on-the-fly key expansion unit and a highly integrated encryption/decryption datapath. The compact on-the-fly key expansion unit is achieved by sharing expansion processes of different key lengths. The integrated data datapath shares hardware resources between encryption and decryption. After manufactured in 90nm CMOS technology, the area of the chip is 15,577 equivalent gates with throughput up to 1.69 Gb/s operating at 131.8 MHz.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117206762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A pixel-shared CMOS image sensor using lateral overflow gate 一种采用横向溢流门的像素共享CMOS图像传感器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326026
Shin Sakai, Y. Tashiro, N. Akahane, R. Kuroda, K. Mizobuchi, S. Sugawa
{"title":"A pixel-shared CMOS image sensor using lateral overflow gate","authors":"Shin Sakai, Y. Tashiro, N. Akahane, R. Kuroda, K. Mizobuchi, S. Sugawa","doi":"10.1109/ESSCIRC.2009.5326026","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326026","url":null,"abstract":"A lateral overflow integration capacitor (LOFIC) based CMOS image sensor sharing two pixels and without row-select transistors has been developed using a newly added lateral overflow gate which directly connects the photodiode and the LOFIC. A 0.18-µm, 2-Poly 3-Metal CMOS technology with a buried pinned photodiode process was employed for the fabrication of the CMOS image sensor having 1/3.3-inch optical format, 1280<sup>H</sup> × 960<sup>V</sup> pixels, and RGB Bayer color filter and on-chip micro-lens on each pixel. The fabricated CMOS image sensor exhibits a high conversion gain of 84-µV/e<sup>-</sup> and a high full well capacity of 6.9 × 10<sup>4</sup>-e<sup>-</sup> in spite of its pixel size of 3.0 × 3.0-µm<sup>2</sup>.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124380489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems 超低功耗SRAM和低活动率数字系统的亚阈值SCL
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325939
A. Tajalli, Y. Leblebici
{"title":"Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems","authors":"A. Tajalli, Y. Leblebici","doi":"10.1109/ESSCIRC.2009.5325939","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325939","url":null,"abstract":"The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS circuits is more pronounced, subthreshold SCL (STSCL) can be used effectively for reducing the power consumption. An STSCL-based static random-access memory (SRAM) array has been implemented to demonstrate the performance of this topology for ultra-low-power consumption and low-activity-rate digital circuits. A novel 9T memory cell has been developed to reduce the stand-by (leakage) current to 10pA/cell while the SRAM array is operating at 2.1MHz clock frequency. The power consumption benefits of the proposed circuit style can be maintained in nanometer CMOS technology nodes.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122716490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A self-adaptive switched-capacitor voltage converter with dynamic input load control for energy harvesting 具有动态输入负载控制的自适应开关电容电压变换器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325937
D. Maurath, Y. Manoli
{"title":"A self-adaptive switched-capacitor voltage converter with dynamic input load control for energy harvesting","authors":"D. Maurath, Y. Manoli","doi":"10.1109/ESSCIRC.2009.5325937","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325937","url":null,"abstract":"This paper presents an implementation of a fully-integrated switched capacitor voltage converter with self-adjusting source loading. A charge control unit ensures improved load matching to the power source, which can be an RFID antenna or vibration energy harvesting generator. In conjunction with an adaptive stacking scheme voltage-up conversion is also realized leading to capacitor storage voltages which are higher than the generator voltage amplitudes. This and the improved load matching result in a higher generator output power. In addition, due to the switched capacitor charge pump no diode for rectification is necessary. The converter design is completely implemented and fully-integrated in a standard 0.35 µm twin-well CMOS process. Generator powers of up to 780 µW can be treated, and maximum conversion efficiency is close to 48%. Input voltage amplitudes are possible between 0.5 V – 2.5 V , while the supply voltage range is 0.9 V – 3.6 V.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115583010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Sub-1V input single-inductor dual-output (SIDO) DC-DC converter with adaptive load-tracking control (ALTC) for single-cell-powered system 基于自适应负载跟踪控制(ALTC)的亚1v输入单电感双输出(SIDO) DC-DC变换器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325988
Ming-Hsin Huang, Yu-Nong Tsai, Yu-Huei Lee, Shih-Jung Wang, Ke-Horng Chen, Ying-Hsi Lin, G. Ma
{"title":"Sub-1V input single-inductor dual-output (SIDO) DC-DC converter with adaptive load-tracking control (ALTC) for single-cell-powered system","authors":"Ming-Hsin Huang, Yu-Nong Tsai, Yu-Huei Lee, Shih-Jung Wang, Ke-Horng Chen, Ying-Hsi Lin, G. Ma","doi":"10.1109/ESSCIRC.2009.5325988","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325988","url":null,"abstract":"In this paper, a sub-1V input single-inductor dual-output (SIDO) DC-DC converter with an adaptive load-tracking control (ALTC) technique is proposed for single-cell-powered portable devices. The ALTC technique adaptively and accurately adjusts storage charge in form of the inductor current according to actual load condition without wasting surplus charge and increasing cross-regulation through the use of minimized the number of switch and optimum current sequence. A current-mode ring oscillator with a self-bias current source (SBCS) circuit is proposed to replace conventional startup oscillator to produce a nearly constant system clock. The test chip was fabricated by TSMC 0.25 µm 2.5 V/5 V BCD process and experimental results show a high efficiency of 92 % and a cross- regulation smaller than 10 mV.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114466401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A single-chip RF tuner / OFDM demodulator for mobile digital TV application 用于移动数字电视的单芯片射频调谐器/ OFDM解调器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326017
Y. Takamatsu, R. Fujimoto, T. Sekine, T. Yasuda, M. Nakamura, T. Hirakawa, M. Ishii, M. Hayashi, H. Ito, Yoko Wada, T. Imayama, Tatsuro Oomoto, Y. Ogasawara, Masaki Nishikawa, Y. Yoshida, Kenji Yoshioka, S. Saigusa, H. Yoshida, N. Itoh
{"title":"A single-chip RF tuner / OFDM demodulator for mobile digital TV application","authors":"Y. Takamatsu, R. Fujimoto, T. Sekine, T. Yasuda, M. Nakamura, T. Hirakawa, M. Ishii, M. Hayashi, H. Ito, Yoko Wada, T. Imayama, Tatsuro Oomoto, Y. Ogasawara, Masaki Nishikawa, Y. Yoshida, Kenji Yoshioka, S. Saigusa, H. Yoshida, N. Itoh","doi":"10.1109/ESSCIRC.2009.5326017","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326017","url":null,"abstract":"This paper presents the first published single-chip RF tuner / OFDM demodulator for a mobile digital TV application (1-segment broadcasting). To improve the minimum sensitivity, spurious signal suppression techniques are proposed. The single-chip RF tuner / OFDM demodulator using the proposed spurious signal suppression techniques is fabricated using 90nm CMOS technology and total die size is 3.26mm×3.26mm. By suppressing undesired spurious signals, the minimum sensitivity of −98.6dBm is achieved. The optimum current consumption is chosen for the RF tuner by using an adaptive control, the power consumption of the proposed single-chip receiver is only 60mW in medium-signal receiving mode.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115895415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
3D capacitive transmission of analog signals with automatic compensation of the voltage attenuation 三维电容传输模拟信号，具有电压衰减自动补偿功能
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325985
E. Franchi, F. Natali, A. Gnudi, R. Guerrieri, M. Innocenti, L. Ciccarelli, M. Scandiuzzo, R. Canegallo
{"title":"3D capacitive transmission of analog signals with automatic compensation of the voltage attenuation","authors":"E. Franchi, F. Natali, A. Gnudi, R. Guerrieri, M. Innocenti, L. Ciccarelli, M. Scandiuzzo, R. Canegallo","doi":"10.1109/ESSCIRC.2009.5325985","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325985","url":null,"abstract":"An architecture to compensate the voltage attenuation introduced by 3D capacitive coupling is proposed. The scheme is applied to the design of a prototype aimed at demonstrating that 3D technology based on capacitive coupling allows to transmit analog signals as well as digital ones. The scheme is based on a calibration channel which sets the gain of the variable gain amplifiers of signal channels in order to compensate for the voltage attenuation. The prototype is designed in CMOS 90 nm technology. 3D assembling is done at die level using a face to face stacking procedure. Each channel has an area 90x30 µm2 and a power consumption of 1 mW. A gain error within 10% with respect to the nominal value has been measured for a signal amplitude varying from 200 mV to 1 V in the 100 KHz to 20 MHz range.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117234175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A SPAD-based pixel linear array for high-speed time-gated fluorescence lifetime imaging 用于高速时间门控荧光寿命成像的spad像素线性阵列
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325948
L. Pancheri, D. Stoppa
{"title":"A SPAD-based pixel linear array for high-speed time-gated fluorescence lifetime imaging","authors":"L. Pancheri, D. Stoppa","doi":"10.1109/ESSCIRC.2009.5325948","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325948","url":null,"abstract":"A monolithic 64-pixel linear array for Fluorescence Lifetime Imaging applications is presented. Each pixel includes four actively quenched Single Photon Avalanche Diodes, four gated 8-bit counters and is capable of measuring single and double exponential decays. The array has a 34% fill factor, a maximum throughput rate of 320 Mbps, and has been tested up to 40 MHz laser repetition rate. Preliminary fluorescence measurements have been performed obtaining a 6% lifetime precision in 660 µs accumulation time and a very good uniformity among the pixels.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126547659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 74
A 240MHz programmable gain amplifier & filter for ultra low power low-rate UWB receivers 240MHz可编程增益放大器和滤波器，用于超低功耗低速率UWB接收器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326006
S. D’Amico, A. Baschirotto, K. Philips, O. Rousseaux, B. Gyselinckx
{"title":"A 240MHz programmable gain amplifier & filter for ultra low power low-rate UWB receivers","authors":"S. D’Amico, A. Baschirotto, K. Philips, O. Rousseaux, B. Gyselinckx","doi":"10.1109/ESSCIRC.2009.5326006","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326006","url":null,"abstract":"A 90nm-CMOS power-optimized Programmable Gain Amplifier (PGA) for Ultra Low power Low Rate-Ultra Wide Band (LR-UWB) receivers is illustrated. The PGA features a 0-40dB programmable gain range with a 5dB gain-step. In addition it implements a 6th —order 240MHz Bessel lowpass transfer function. The cut-off frequency is about constant, independently on the different gain settings. At 40dB gain, the input 1dBcp is −44.8dBm, and the NF is 14.3dB. The current consumption (1.9mA at 0dB-gain up to 2.9mA at 40dB-gain) is optimized by including the opamp performance in the cell transfer function, and accordingly to the selected gain level.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122258967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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