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2009 Proceedings of ESSCIRC最新文献

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High efficiency buck-boost converter with reduced average inductor current (RAIC) technique 采用降低平均电感电流(RAIC)技术的高效降压-升压变换器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326019
Ping-Ching Huang, Wei-Quan Wu, Hsin-Hsin Ho, Ke-Horng Chen, G. Ma
{"title":"High efficiency buck-boost converter with reduced average inductor current (RAIC) technique","authors":"Ping-Ching Huang, Wei-Quan Wu, Hsin-Hsin Ho, Ke-Horng Chen, G. Ma","doi":"10.1109/ESSCIRC.2009.5326019","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326019","url":null,"abstract":"This paper presents a buck-boost converter with high-efficiency and smooth-transition to extend the battery life of portable devices. The new control topology minimizes the switching and conduction losses at the same time even four switches are used. Therefore, over a wide input voltage range, the proposed buck-boost converter with minimum switching loss like the buck or boost converter can reduce the conduction loss through the use of the reduced average inductor current (RAIC) level. Especially, the converter offers good line/load regulation and thus provides a smooth and stable output voltage without being affected by the decreasing battery voltage. Experimental results show that the output voltage is regulated for the whole battery life time and the output transition is very smooth during mode transition. Besides, the output voltage ripple and the average inductor current are effectively minimized by the proposed control scheme. The peak efficiency is 97% and output voltage ripple is reduced from 100mV to within 10mV.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128043716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A single-chip CMOS UHF RFID Reader transceiver for mobile applications 用于移动应用的单芯片CMOS超高频RFID阅读器收发器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326003
Le Ye, H. Liao, Fei Song, Jiang Chen, Congyin Shi, Chen Li, Junhua Liu, Ru Huang, Jinshu Zhao, Huiling Xiao, Ruiqiang Liu, Xin'an Wang
{"title":"A single-chip CMOS UHF RFID Reader transceiver for mobile applications","authors":"Le Ye, H. Liao, Fei Song, Jiang Chen, Congyin Shi, Chen Li, Junhua Liu, Ru Huang, Jinshu Zhao, Huiling Xiao, Ruiqiang Liu, Xin'an Wang","doi":"10.1109/ESSCIRC.2009.5326003","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326003","url":null,"abstract":"A UHF RFID Reader Transceiver for China standard (840∼925 MHz) as well as meeting the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000–6C is presented. To suppress the large self-jammer from transmitter to receiver, an on-chip self-jammer cancellation (SC) circuits and a fully-integrated DC-offset Cancellation (DCOC) circuits with quickly time-varying cut-off frequency are proposed to kill the self-jammer within 15 µs. Furthermore, a mixer with capacitor cross-coupled (CCC) common-gate input stage and vertical NPN BJT switching stage is proposed to achieve high linearity (−8 dBm P1dB), good wideband matching and low 1/f noise corner. The transmitter integrated with a CMOS class-AB PA of 22 dBm output power in linear mode with 35% PAE, which is suitable for mobile applications, supports the DSB/SSB/PR-ASK modulation schemes and achieves ACPR1 of −45 dBc and ACPR2 of −60 dBc, which satisfies the stringent spectral mask of China local requirements. A sigma-delta PLL with a single LC VCO is also implemented for 250 kHz channel hopping and good phase noise (−126 dBc/Hz at 1MHz offset). The receiver has a sensitivity of down to −77 dBm in the presence of 20 dBm PA output power. The single-chip is implemented in standard 0.18 µm CMOS process. It occupies 13.5 mm2 silicon areas, and consumes 113 mA (without PA) from 1.8V supply voltage.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132916868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An S-band frontend receiver for mobile TV in 65nm CMOS 用于移动电视的65纳米CMOS s波段前端接收器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325963
T. Chalvatzis, K. Vavelidis, N. Kanakaris, I. Vassiliou
{"title":"An S-band frontend receiver for mobile TV in 65nm CMOS","authors":"T. Chalvatzis, K. Vavelidis, N. Kanakaris, I. Vassiliou","doi":"10.1109/ESSCIRC.2009.5325963","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325963","url":null,"abstract":"This paper presents a frontend receiver for S-band mobile TV applications. The direct conversion receiver covers the 2.635–2.66GHz band using a frequency multiplication scheme to generate the LO. The LNA operates either in a digitally controlled gain mode or in a bypass state. The receiver achieves 96dB of maximum gain with a corresponding NF and out-of-band IIP3 of 2.9dB and −8dBm, respectively. The frontend current consumption is 19mA from 1.2V power supply. The receiver is implemented in a 65nm CMOS process.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121098567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power reduction techniques for an 8-core xeon® processor 8核xeon®处理器的功耗降低技术
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326028
S. Rusu, S. Tam, H. Muljono, J. Stinson, D. Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, S. Vora
{"title":"Power reduction techniques for an 8-core xeon® processor","authors":"S. Rusu, S. Tam, H. Muljono, J. Stinson, D. Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, S. Vora","doi":"10.1109/ESSCIRC.2009.5326028","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326028","url":null,"abstract":"This paper presents the power reduction and management techniques for the 45nm, 8-core Nehalem-EX processor. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. Clock and power gating minimize power consumed by disabled blocks. An on-die microcontroller manages voltage and frequency operating points, as well as power and thermal events. Idle power is reduced by shutting off the un-terminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121416681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An ambient light adaptive subretinal stimulator 环境光自适应视网膜下刺激器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325980
Liu Liu, Jürgen Wünschmann, Naser Pour Aryan, Amr Zohny, M. Fischer, Steffen Kibbel, A. Rothermel
{"title":"An ambient light adaptive subretinal stimulator","authors":"Liu Liu, Jürgen Wünschmann, Naser Pour Aryan, Amr Zohny, M. Fischer, Steffen Kibbel, A. Rothermel","doi":"10.1109/ESSCIRC.2009.5325980","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325980","url":null,"abstract":"This paper presents a subretinal stimulator which is able to automatically adapt to varying ambient light levels. Stimulation timing and intensity are controlled using an input amplifier with an offset current cancellation circuitry to eliminate offset current imposed on the pixel amplifier for accurate stimulation control and optimized power consumption. In order to enable the chip to operate over a wide range of luminance conditions without manual tuning, automatic ambient light adaptation is required. Comparing the local photosensor output with a global luminance reference signal forms the basis of the adaptation mechanism. Global brightness information is obtained by logarithmic conversion of the summed photocurrents to generate a global luminance reference voltage. The chip has been realized in Austria Micro Systems 0.35µm CMOS Opto technology.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116657303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend 一个数字校准的14位线性100毫秒/秒的流水线ADC与宽带采样前端
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325956
L. Luo, Kaihui Lin, Long Cheng, Liren Zhou, Fan Ye, Junyan Ren
{"title":"A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend","authors":"L. Luo, Kaihui Lin, Long Cheng, Liren Zhou, Fan Ye, Junyan Ren","doi":"10.1109/ESSCIRC.2009.5325956","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325956","url":null,"abstract":"A 14-bit 100-MS/s pipelined ADC in 0.18 µm 1P6M CMOS process is presented. A new sampling technique is introduced which achieves high linearity over wide bandwidth by eliminating the major sources of distortion at low and high input frequencies. The ADC uses digital background calibration, featuring a shuffled-dithering scheme, to obtain a DNL of +0.18/−0.18 LSB and an INL of +1.1/−0.6 LSB. It achieves over 85dB SFDR and 65dB SNDR within the first Nyquist zone, maintains over 74 dB SFDR and 63 dB SNDR for input signals up to 400 MHz and consumes 220 mW at 1.8 V supply.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114485003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
A 1-V 84-dB DR 1-MHz bandwidth cascade 3–1 Delta-Sigma ADC in 65-nm CMOS 1-V 84-dB DR 1-MHz带宽级联3-1 Delta-Sigma ADC, 65nm CMOS
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326016
Koen Cornelissens, M. Steyaert
{"title":"A 1-V 84-dB DR 1-MHz bandwidth cascade 3–1 Delta-Sigma ADC in 65-nm CMOS","authors":"Koen Cornelissens, M. Steyaert","doi":"10.1109/ESSCIRC.2009.5326016","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326016","url":null,"abstract":"This paper presents a switched-capacitor ΔΣ analog-to-digital converter, achieving a dynamic range of 84 dB and a bandwidth of 1 MHz for a power consumption of 17 mW. A cascade 3–1 topology allows aggressive noise-shaping without imposing too stringent specifications on the amplifiers. The design is implemented in a 1 V, 65 nm standard CMOS technology. The use of a novel symmetrical bootstrapped switch solves the non-linearity issues of low-voltage transmission gates. The higher flicker noise of nanoscale CMOS technologies is reduced by applying chopping to the first amplifier input pair.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114499045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 10Gb/s NRZ receiver with feedforward equalizer and glitch-free phase-frequency detector 带有前馈均衡器和无故障相频检测器的10Gb/s NRZ接收机
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325958
Ali Kiaei, M. Bohsali, Ahmad Bahai, T. Lee
{"title":"A 10Gb/s NRZ receiver with feedforward equalizer and glitch-free phase-frequency detector","authors":"Ali Kiaei, M. Bohsali, Ahmad Bahai, T. Lee","doi":"10.1109/ESSCIRC.2009.5325958","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325958","url":null,"abstract":"A 10Gb/s NRZ receiver with feedforward equalizer and CDR is described. The CDR incorporates an LC oscillator with a range of 8.3 to 11.1 GHz and a new glitch-free binary PFD. The glitch-free architecture minimizes the jitter generation of the CDR and increases jitter tolerance. The CDR loop employs a V/I converter with two independent charge-pumps for FD and PD signals to achieve fast acquisition and low jitter generation simultaneously.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127936882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-noise ESD-protected 24 GHz receiver for radar applications in SiGe:C technology 采用SiGe:C技术的低噪声防静电24 GHz雷达接收机
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326009
V. Issakov, H. Knapp, F. Magrini, A. Thiede, W. Simbürger, L. Maurer
{"title":"Low-noise ESD-protected 24 GHz receiver for radar applications in SiGe:C technology","authors":"V. Issakov, H. Knapp, F. Magrini, A. Thiede, W. Simbürger, L. Maurer","doi":"10.1109/ESSCIRC.2009.5326009","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326009","url":null,"abstract":"This paper presents a low-noise ESD-protected 24 GHz receiver in Infineon's B7HF200 SiGe technology. The fully differential circuit integrates a Low Noise Amplifier (LNA), two low-noise mixers and polyphase filters for on-chip quadrature generation. The front-end has been designed to meet high robustness requirements for industrial or automotive applications. It offers ESD hardness of 1.5 A Transmission Line Pulse (TLP) failure current on the RF pins, which corresponds to HBM protection above 2 kV. Furthermore, the performance variation of key parameters has been analyzed in measurement over a wide range of temperatures from −40 °C to 125 °C. The receiver offers a conversion gain of 21.5 dBand a very low noise figure of 3.1 dB at the center frequency of 24 GHz. The circuit exhibits a linearity of −20.5 dBm and −11 dBm input-referred 1dB compression point and IIP3, respectively. The front-end consumes 39 mA from a single 3.3 Vsupply. The chip area including pads is 1 mm2.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129560068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A parallel 32×32 time-to-digital converter array fabricated in a 130 nm imaging CMOS technology 采用130纳米成像CMOS技术制造的平行32×32时间-数字转换器阵列
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326021
M. Gersbach, Y. Maruyama, E. Labonne, J. Richardson, R. Walker, L. Grant, R. Henderson, F. Borghetti, D. Stoppa, E. Charbon
{"title":"A parallel 32×32 time-to-digital converter array fabricated in a 130 nm imaging CMOS technology","authors":"M. Gersbach, Y. Maruyama, E. Labonne, J. Richardson, R. Walker, L. Grant, R. Henderson, F. Borghetti, D. Stoppa, E. Charbon","doi":"10.1109/ESSCIRC.2009.5326021","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326021","url":null,"abstract":"We report on the design and characterization of a 32 × 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at ± 0.4 and ±1.2 LSBs respectively. The TDC array was fabricated with a pitch of 50µm in both directions and with a total TDC area of less than 2000µm2. The characteristics of the array make it an excellent candidate for in-pixel TDC in time-resolved imagers for applications such as 3-D imaging and fluorescence lifetime imaging microscopy (FLIM).","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121961480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 81
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