L. Luo, Kaihui Lin, Long Cheng, Liren Zhou, Fan Ye, Junyan Ren
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引用次数: 34
摘要
提出了一种基于0.18µm 1P6M CMOS工艺的14位100 ms /s流水线ADC。介绍了一种新的采样技术，通过消除低频率和高频率输入失真的主要来源，在宽带宽上实现高线性度。ADC使用数字背景校准，具有洗牌抖动方案，可获得+0.18/−0.18 LSB的DNL和+1.1/−0.6 LSB的INL。它在第一个Nyquist区域内实现超过85dB的SFDR和65dB的SNDR，在高达400mhz的输入信号中保持超过74db的SFDR和63db的SNDR，在1.8 V电源下消耗220 mW。
A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend
A 14-bit 100-MS/s pipelined ADC in 0.18 µm 1P6M CMOS process is presented. A new sampling technique is introduced which achieves high linearity over wide bandwidth by eliminating the major sources of distortion at low and high input frequencies. The ADC uses digital background calibration, featuring a shuffled-dithering scheme, to obtain a DNL of +0.18/−0.18 LSB and an INL of +1.1/−0.6 LSB. It achieves over 85dB SFDR and 65dB SNDR within the first Nyquist zone, maintains over 74 dB SFDR and 63 dB SNDR for input signals up to 400 MHz and consumes 220 mW at 1.8 V supply.
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