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A CMOS ESD-protected RF front-end for UWB receiver 一种用于UWB接收机的CMOS防静电射频前端
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325951
B. Shi, M. Chia
{"title":"A CMOS ESD-protected RF front-end for UWB receiver","authors":"B. Shi, M. Chia","doi":"10.1109/ESSCIRC.2009.5325951","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325951","url":null,"abstract":"This paper presents a CMOS receiver front-end for ultra-wideband (UWB) wireless applications within the 3.1–10.6 GHz band. Fabricated in a 0.13um CMOS technology, the packaged and ESD-protected receiver integrates a broadband low-noise amplifier (LNA), a quadrature downconversion mixer, and local oscillator (LO) amplifiers. The LNA employs a noise-canceling technique to decouple input match from noise figure (NF) while having ESD and package parasitics absorbed into a wideband input matching network. Variable-gain methods are developed for the LNA to obtain gain switching. The proposed double-balanced quadrature mixer has an active balun and a voltage buffer embedded so that it can be directly driven by the single-ended LNA. Drawing 22 mA from 1.5V, the RFIC provides a voltage conversion gain of 29 dB with an input IP3 of −13.5 dBm and an input IP2 of 24 dBm. Over the entire UWB band, an NF of 4.9–8.8 dB and an S11 ≪−7 dB were measured.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130954654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A MOS current-mode buck DC-DC Converter with a 240-kHz loop bandwidth and unaltered frequency characteristics using a quadratic and input-voltage-dependent compensation slope 一种MOS电流型降压DC-DC变换器，环路带宽为240khz，频率特性不变，采用二次型和输入电压相关的补偿斜率
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325976
Y. Sugimoto
{"title":"A MOS current-mode buck DC-DC Converter with a 240-kHz loop bandwidth and unaltered frequency characteristics using a quadratic and input-voltage-dependent compensation slope","authors":"Y. Sugimoto","doi":"10.1109/ESSCIRC.2009.5325976","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325976","url":null,"abstract":"In this study, we verified that a quadratic slope was the best-fit compensation slope for the current feedback loop of a current-mode DC-DC converter by considering the stability of the inductor current when the current disturbance was applied. We also verified that the introduction of the input voltage dependency to the quadratic slope enabled the frequency characteristics of the current feedback loop to remain completely constant without depending on the input and output voltage change of a DC-DC converter. The test chip of a MOS current-mode buck DC-DC converter using a 0.35-µm CMOS process and a 5-MHz clock realized two loop frequency bandwidths of 130 kHz and 240 kHz and was operated in two different input and output voltage settings for each frequency bandwidth. As a result, the unaltered gain and phase frequency characteristics were obtained for two different settings in each frequency bandwidth.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121918442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A fully on-chip LDO voltage regulator for remotely powered cortical implants 一种用于远程供电皮质植入物的全片上LDO电压调节器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325969
V. Majidzadeh, A. Schmid, Y. Leblebici
{"title":"A fully on-chip LDO voltage regulator for remotely powered cortical implants","authors":"V. Majidzadeh, A. Schmid, Y. Leblebici","doi":"10.1109/ESSCIRC.2009.5325969","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325969","url":null,"abstract":"This article presents a fully on-chip low-power low drop-out (LDO) voltage regulator dedicated to remotely powered wireless cortical implants. This regulator is stable over the full range of alternating current without the need of dedicated active circuitry and increase in ground current. A new compensation technique is proposed to improve PSRR beyond the performance which can be achieved by regular cascode compensation technique. Measurement results show that the regulator has a load regulation of 0.175V/A, a line regulation of 0.024%, and a PSRR of 37dB at 1MHz power carrier frequency. The output of the regulator settles within 10-bit accuracy of the nominal voltage (1.8V) within 1.6µµs, at full load transition. The output spot noise at 100Hz and 100kHz are 1.1µV/sqrt (Hz) and 390nV/sqrt (Hz), respectively. The total ground current including the bandgap reference circuit is 28µA and the active chip area measures 290µm×360µm in 0.18µm CMOS technology.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131507507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Extraneous-light resistant multipixel range sensor based on a low-power correlating pixel-circuit 基于低功耗相关像素电路的抗杂光多像素距离传感器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326018
G. Zach, M. Davidović, H. Zimmermann
{"title":"Extraneous-light resistant multipixel range sensor based on a low-power correlating pixel-circuit","authors":"G. Zach, M. Davidović, H. Zimmermann","doi":"10.1109/ESSCIRC.2009.5326018","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326018","url":null,"abstract":"This work covers a correlation-based, optical time-of-flight matrix range sensor which is able to suppress ambient light up to 150klx full-electronically and autonomously in each single pixel. The CMOS-compatible sensor features 16×16 pixels and permits distance measurements with a standard deviation of 1cm (5cm) up to 1m (3.2m), while the linearity error is within ±2cm for the entire measurement range within a measurement time of 50ms per distance point. A 0.9W LED source is used to illuminate the field of view with near-infrared light, which is modulated at 10MHz. In this design, the current consumption could be reduced from 100µA to 2µA per pixel, while increasing the distance measurement performance at the same time.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131500455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A real-time image recognition system using a global directional-edge-feature extraction VLSI processor 采用全局方向边缘特征提取VLSI处理器的实时图像识别系统
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325996
Hongbo Zhu, T. Shibata
{"title":"A real-time image recognition system using a global directional-edge-feature extraction VLSI processor","authors":"Hongbo Zhu, T. Shibata","doi":"10.1109/ESSCIRC.2009.5325996","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325996","url":null,"abstract":"A directional-edge-feature-based real-time image recognition system has been developed. By employing a digital-pixel-sensor-embedded feature extraction VLSI processor, the delay due to the image data transfer between the image sensor and the feature extraction circuits, the most serious bottleneck in such systems, has been reduced dramatically. Parallel feature vector-generation and template-matching processor functions implemented on an FPGA further accelerate the processing speed. As a result, the latency between the image capture and the final recognition has been reduced to only 906 µs, making this system suitable for time critical applications. In addition, the capability of the system for automatic adaptation to more significant features has also been experimentally demonstrated.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122942071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Designing ultra-low voltage PLL Using a bulk-driven technique 采用体积驱动技术设计超低电压锁相环
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325983
Ting-Sheng Chao, Y. Lo, Wei-Bin Yang, Kuo-Hsing Cheng
{"title":"Designing ultra-low voltage PLL Using a bulk-driven technique","authors":"Ting-Sheng Chao, Y. Lo, Wei-Bin Yang, Kuo-Hsing Cheng","doi":"10.1109/ESSCIRC.2009.5325983","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325983","url":null,"abstract":"This paper describes an ultra-low voltage phase-locked loop (PLL) using a bulk-driven technique. The architecture of the proposed PLL employs the bulk-input technique to produce a voltage-controlled oscillator (VCO) and the forward-body-bias scheme to produce a divider. This approach effectively reduces the threshold voltage of the MOSFETs, enabling the PLL to be operated at an ultra-low voltage. The chip is fabricated in a 0.13-µm standard CMOS process with a 0.5V power supply voltage. The measurement results demonstrate that this PLL can operate from 360 to 610MHz with a 0.5V power supply voltage. At 550MHz, the measured rms jitter and peak-to-peak jitter are 8.01ps and 56.36ps, respectively. The total power consumption of the PLL is 1.25mW and the active die area of PLL is 0.04mm2.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121928914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A Microprogrammable Memory Controller for high-performance dataflow applications 用于高性能数据流应用的微可编程存储器控制器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325981
Jérôme Martin, C. Bernard, F. Clermidy, Y. Durand
{"title":"A Microprogrammable Memory Controller for high-performance dataflow applications","authors":"Jérôme Martin, C. Bernard, F. Clermidy, Y. Durand","doi":"10.1109/ESSCIRC.2009.5325981","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325981","url":null,"abstract":"High-performance embedded dataflow systems require intensive data manipulation involving synchronization, buffering, duplication and reordering. Our Microprogrammable Memory Controller (MMC) is designed to handle these tasks more efficiently than the data processing cores. Dataflow management for several computing cores is combined in a single MMC. This reduces the global complexity and memory of the system. The MMC has been implemented in a 65nm low-power CMOS integrated circuit for baseband processing of OFDMA communications. It achieves a bandwidth of 24.6Gbps @385MHz, with an average 38mW power consumption.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115073910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 32x32-pixel array with in-pixel photon counting and arrival time measurement in the analog domain 一个32x32像素阵列，具有像素内光子计数和模拟域的到达时间测量
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325970
D. Stoppa, F. Borghetti, J. Richardson, R. Walker, L. Grant, R. Henderson, M. Gersbach, E. Charbon
{"title":"A 32x32-pixel array with in-pixel photon counting and arrival time measurement in the analog domain","authors":"D. Stoppa, F. Borghetti, J. Richardson, R. Walker, L. Grant, R. Henderson, M. Gersbach, E. Charbon","doi":"10.1109/ESSCIRC.2009.5325970","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325970","url":null,"abstract":"A Time-to-Amplitude Converter (TAC) with embedded analog-to-digital conversion is implemented in a 130-nm CMOS imaging technology. The proposed module is conceived for Single-Photon Avalanche Diode imagers and can operate both as a TAC or as an analog counter, thus allowing both time-correlated or time-uncorrelated imaging operation. A single-ramp, 8-bit ADC with two memory banks to allow high-speed, time-interleaved operation is also included within each module. A 32x32-TACs array has been fabricated with a 50-µm pitch in order prove the highly parallel operation and to test uniformity and power consumption issues. The measured time resolution (LSB) is of 160 ps on a 20-ns time range with a uniformity across the array within ±2LSBs, while DNL and INL are 0.7LSB and 1.9LSB respectively. The average power consumption is below 300µW/pixel when running at 500k measurements per second.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123143022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 110
A 1x1 802.11n WLAN SoC with fully integrated RF front-end utilizing PA linearization 1x1 802.11n WLAN SoC，具有完全集成的射频前端，采用PA线性化
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325998
M. Terrovitis, M. Mack, J. Hwang, Brian J. Kaczynski, G. Tseng, B. Wang, S. Mehta, D. Su
{"title":"A 1x1 802.11n WLAN SoC with fully integrated RF front-end utilizing PA linearization","authors":"M. Terrovitis, M. Mack, J. Hwang, Brian J. Kaczynski, G. Tseng, B. Wang, S. Mehta, D. Su","doi":"10.1109/ESSCIRC.2009.5325998","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325998","url":null,"abstract":"A 1x1 2.4GHz 802.11n draft compliant radio SoC with fully integrated front-end is presented. A linearized power amplifier is merged with a low noise amplifier to form an RF front end with built-in transmit/receive switch functionality. In HT20 mode, the radio can transmit 19.4dBm spectral mask compliant power and 18.4dBm EVM-compliant power at 65Mbps rate. The sensitivity from the port shared with the PA is −97 dBm at 1Mbps rate.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124242702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An integrated common-mode feedback topology for multi-frequency bioimpedance imaging 用于多频生物阻抗成像的集成共模反馈拓扑
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325943
M. Rahal, A. Demosthenous, R. Bayford
{"title":"An integrated common-mode feedback topology for multi-frequency bioimpedance imaging","authors":"M. Rahal, A. Demosthenous, R. Bayford","doi":"10.1109/ESSCIRC.2009.5325943","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325943","url":null,"abstract":"One of the key limitations in medical impedance imaging and bio-impedance measurements is common-mode errors. We present an integrated common-mode feedback topology which reduces these errors for use in a bio-imaging system for in-vivo monitoring of neonate lung function (10–200 kHz current injection frequency). A frequency-selective feedback network is described which reduces the common-mode voltage due to electrode impedance mismatch at the input of the differential amplifier. The theory and key design blocks are presented. The circuit was implemented in a 5-V 0.35-µm CMOS technology, occupying an area of 0.75 mm2 and dissipating about 20 mW. Experiments were conducted using, an RC model of the electrodes, and ECG electrodes on the forearm to demonstrate the working of the integrated circuit. Measured results show that the common-mode signal is reduced by 85%, 75%, 70% and 65% at 10kHz, 50kHz, 100 kHz and 200 kHz, respectively.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132674037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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