{"title":"采用全局方向边缘特征提取VLSI处理器的实时图像识别系统","authors":"Hongbo Zhu, T. Shibata","doi":"10.1109/ESSCIRC.2009.5325996","DOIUrl":null,"url":null,"abstract":"A directional-edge-feature-based real-time image recognition system has been developed. By employing a digital-pixel-sensor-embedded feature extraction VLSI processor, the delay due to the image data transfer between the image sensor and the feature extraction circuits, the most serious bottleneck in such systems, has been reduced dramatically. Parallel feature vector-generation and template-matching processor functions implemented on an FPGA further accelerate the processing speed. As a result, the latency between the image capture and the final recognition has been reduced to only 906 µs, making this system suitable for time critical applications. In addition, the capability of the system for automatic adaptation to more significant features has also been experimentally demonstrated.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"140 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A real-time image recognition system using a global directional-edge-feature extraction VLSI processor\",\"authors\":\"Hongbo Zhu, T. Shibata\",\"doi\":\"10.1109/ESSCIRC.2009.5325996\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A directional-edge-feature-based real-time image recognition system has been developed. By employing a digital-pixel-sensor-embedded feature extraction VLSI processor, the delay due to the image data transfer between the image sensor and the feature extraction circuits, the most serious bottleneck in such systems, has been reduced dramatically. Parallel feature vector-generation and template-matching processor functions implemented on an FPGA further accelerate the processing speed. As a result, the latency between the image capture and the final recognition has been reduced to only 906 µs, making this system suitable for time critical applications. In addition, the capability of the system for automatic adaptation to more significant features has also been experimentally demonstrated.\",\"PeriodicalId\":258889,\"journal\":{\"name\":\"2009 Proceedings of ESSCIRC\",\"volume\":\"140 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Proceedings of ESSCIRC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2009.5325996\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Proceedings of ESSCIRC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2009.5325996","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A real-time image recognition system using a global directional-edge-feature extraction VLSI processor
A directional-edge-feature-based real-time image recognition system has been developed. By employing a digital-pixel-sensor-embedded feature extraction VLSI processor, the delay due to the image data transfer between the image sensor and the feature extraction circuits, the most serious bottleneck in such systems, has been reduced dramatically. Parallel feature vector-generation and template-matching processor functions implemented on an FPGA further accelerate the processing speed. As a result, the latency between the image capture and the final recognition has been reduced to only 906 µs, making this system suitable for time critical applications. In addition, the capability of the system for automatic adaptation to more significant features has also been experimentally demonstrated.