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2009 Proceedings of ESSCIRC最新文献

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A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving 一个2.5GHz, 6.9mW ΔΣ调制器，标准单元设计，45nm-LP CMOS，采用时间交错
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325960
P. Madoglio, A. Ravi, L. Cuellar, S. Pellerano, P. Seddighrad, Ismael Lomeli, Y. Palaskas
{"title":"A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving","authors":"P. Madoglio, A. Ravi, L. Cuellar, S. Pellerano, P. Seddighrad, Ismael Lomeli, Y. Palaskas","doi":"10.1109/ESSCIRC.2009.5325960","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325960","url":null,"abstract":"A technique to implement time-interleaved digital ΔΣ modulators using standard cells and digital synthesis tools is presented. Time interleaving allows clocking of the standard cell blocks at submultiples of the final sampling rate fs. Additional delay stages are used to segment the time-interleaved/pipelined MASH ΔΣ topology into reduced complexity sub-blocks, each with independent critical paths. A prototype IC has been fabricated in digital CMOS 45nm-LP: it has been validated at 2.5GHz, while consuming 6.9mW from a 1.1V supply, and at 3.3GHz increasing the nominal supply to 1.2V.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132808042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS 2.89mW 50GOPS 16×16 16核90nm CMOS MIMO球面解码器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325957
Chia-Hsiang Yang, D. Markovic
{"title":"A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS","authors":"Chia-Hsiang Yang, D. Markovic","doi":"10.1109/ESSCIRC.2009.5325957","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325957","url":null,"abstract":"A 16-core multi-input multi-output (MIMO) decoder for agile communication systems is implemented in a low-VT 90nm CMOS technology. This chip implements the sphere decoding algorithm and is highly flexible to support multiple configurations: antenna arrays from 2×2 to 16×16, modulations from BPSK to 64QAM, and up to 128 data streams. Operating at 16MHz, the chip provides 50GOPS (12-bit add equivalent) in the 16×16, 64QAM mode. It consumes 2.89mW of power with a 321mV supply voltage, resulting in a power efficiency of 17.3GOPS/mW. At 256MHz, the peak data rate exceeds 1.5Gbps over a 16MHz channel.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114840178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
High efficiency DC-DC buck converter with 60/120-MHz switching frequency and 1-A output current 高效率DC-DC降压变换器，开关频率为60/120 mhz，输出电流为1a
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325999
M. Belloni, E. Bonizzoni, F. Maloberti
{"title":"High efficiency DC-DC buck converter with 60/120-MHz switching frequency and 1-A output current","authors":"M. Belloni, E. Bonizzoni, F. Maloberti","doi":"10.1109/ESSCIRC.2009.5325999","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325999","url":null,"abstract":"This DC-DC buck converter is able to operate up to 120-MHz switching frequency with peak power efficiency of 87% for 75% duty cycle and 93% at 60 MHz. Key feature of this design is a new control method that replaces the conventional op-amp based scheme. The proposed circuit uses a current-mode control and a voltage-to-pulse converter for the PWM. The circuit, fabricated using a 0.18-µm CMOS technology, reaches a peak load regulation of 20 mV/V and line regulation of 0.5 mV/V at 300 mA. The used 36-nH inductance and 4.7-µF capacitor are suitable for SiP realizations.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"500 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116203929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A resonant-clock 200MHz ARM926EJ-STM microcontroller 谐振时钟200MHz ARM926EJ-STM微控制器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325961
A. Ishii, J. C. Kao, V. Sathe, M. Papaefthymiou
{"title":"A resonant-clock 200MHz ARM926EJ-STM microcontroller","authors":"A. Ishii, J. C. Kao, V. Sathe, M. Papaefthymiou","doi":"10.1109/ESSCIRC.2009.5325961","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325961","url":null,"abstract":"An ARM926EJ-STM microcontroller with a fully resonant clock distribution network and 16KB data and instruction caches has been implemented in 130nm bulk silicon. Workloads execute successfully across process and temperature corners, and at room temperature, typical-process chips run at clock speeds up to 200MHz with 1.2V supply. At resonance, the microcontroller core dissipates 0.23mW/MHz, recovering 85% of the energy in its clock distribution network. Total power savings range from 20% to 35%, depending on application workload and computation profile.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124008128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
The impact of semiconductor packaging technologies on system integration an overview 半导体封装技术对系统集成的影响综述
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325925
C. Cognetti
{"title":"The impact of semiconductor packaging technologies on system integration an overview","authors":"C. Cognetti","doi":"10.1109/ESSCIRC.2009.5325925","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325925","url":null,"abstract":"We are crossing the threshold of the third revolution in semiconductor packaging. In the '80s, Surface Mount Technology (SMT) had major impact on size reduction of all electronic systems. In the '90s, Ball Grid Array (BGA) has been introduced, whose latest evolution allows further dramatic steps in miniaturization, with cost effective production of 3- dimensional structures and the integration of a large number of passive and active devices in the same package (System in Package - SiP). 3D-BGA platform is now well established and offers an alternative to System on Chip (SoC), i.e. the full integration at chip level. With the additional possibility of combining “heterogeneous” devices [1]. But BGA is getting close to its intrinsic limits and will not be able to serve the requirements (size, speed, thermal dissipation, cost) of next advanced systems, like future wireless applications. At present, most of R&D effort is dedicated to the development of new concepts, mixing conventional assembly and “on wafer” processes. The result is the “3D Wafer Level” platform, which will provide unprecedented levels of integration, with several breakthroughs in design, manufacturing infrastructure, supply chain.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122732523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
FinFET RF receiver building blocks operating above 10 GHz 工作在10ghz以上的FinFET射频接收器模块
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325986
D. Siprak, P. Wambacq, B. Parvais, A. Mercha, M. Fulde, Jesenka Veledar Kruger, M. Dehan, S. Decoutere
{"title":"FinFET RF receiver building blocks operating above 10 GHz","authors":"D. Siprak, P. Wambacq, B. Parvais, A. Mercha, M. Fulde, Jesenka Veledar Kruger, M. Dehan, S. Decoutere","doi":"10.1109/ESSCIRC.2009.5325986","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325986","url":null,"abstract":"A FinFET VCO and a differential LNA operating at 17 GHz are presented. The LNA contains on-chip input and output baluns, the input balun for the conversion of the single-ended antenna signal, and it achieves a gain of 9.4 dB and a noise figure of 6.6 dB when the output balun is deembedded; the power consumption is 26 mW from a 1V supply. The VCO oscillates between 15.3 – 17.1 GHz and reaches a phase noise of −94 dBc/Hz at 1 MHz frequency offset with a power consumption of 7.5 mW. Device characterization data for circuit assessment and performance extrapolation is additionally presented.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122853437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead 具有1.5周期延迟开销的600MHz电荷恢复FIR滤波器
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325975
J. C. Kao, Wei-Hsiang Ma, V. Sathe, M. Papaefthymiou
{"title":"A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead","authors":"J. C. Kao, Wei-Hsiang Ma, V. Sathe, M. Papaefthymiou","doi":"10.1109/ESSCIRC.2009.5325975","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325975","url":null,"abstract":"We present a 14-tap 8-bit FIR chip designed using a novel charge-recovery logic family with only 1.5 cycles of additional latency over the best possible static CMOS design. Fabricated in a 0.13µm CMOS process, the chip operates in the 365—600MHz range with a 3nH on-chip inductor. At its resonant frequency of 466MHz, it dissipates 39.1mW and recovers 45% of the energy supplied to it.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130399994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Challenges and prospects of RF oscillators using silicon resonant tunneling diodes 硅谐振隧道二极管射频振荡器的挑战与展望
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325989
E. Buccafurri, A. Medjahdi, F. Calmon, R. Clerc, M. Pala, A. Poncet, G. Ghibaudo
{"title":"Challenges and prospects of RF oscillators using silicon resonant tunneling diodes","authors":"E. Buccafurri, A. Medjahdi, F. Calmon, R. Clerc, M. Pala, A. Poncet, G. Ghibaudo","doi":"10.1109/ESSCIRC.2009.5325989","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325989","url":null,"abstract":"Advanced SOI and strained-SOI (s-SOI) technologies may be an alternative option to integrate Resonant Tunneling Diodes (RTD) in a silicon process. To investigate the expected performances of such technologies, a complete DC and AC compact model of silicon RTD has been proposed, and implemented in a circuit simulator. RTD based RF oscillators have been simulated and compared to more conventional silicon circuits. Even if SOI based RTD offers lower performances than their III-V counterparts, it turns out that extremely low power RF oscillator at 20 GHz can be realized on silicon using this technology.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128709667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low noise, high gain, highly linear mixer for 77 GHz automotive radar applications in SiGe:C bipolar technology 一款低噪声、高增益、高线性混频器，适用于77 GHz汽车雷达应用，采用SiGe:C双极技术
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5326012
Shoujun Yang, H. Forstner, Günther Haider, Harald Kainmueller, K. Aufinger, L. Maurer, R. Hagelauer
{"title":"A low noise, high gain, highly linear mixer for 77 GHz automotive radar applications in SiGe:C bipolar technology","authors":"Shoujun Yang, H. Forstner, Günther Haider, Harald Kainmueller, K. Aufinger, L. Maurer, R. Hagelauer","doi":"10.1109/ESSCIRC.2009.5326012","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5326012","url":null,"abstract":"This paper presents a modified Gilbert type mixer which is fabricated in a 200 GHz fT SiGe:C bipolar technology and well suited for 77 GHz bi-static automotive radar applications. The measured single sideband noise figure (NFSSB), conversion gain (CG), and input-referred 1 dB compression point (ICP) of this mixer are 10.8 dB, 21.5 dB, and −5 dBm, respectively. The current consumption is 21 mA under 3.3 V power supply. This mixer shows state-of-the-art noise figure, conversion gain traded-off with 1 dB compression point, and low power consumption.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128775700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Pulsed time-of-flight 3D-CMOS imaging using photogate-based active pixel sensors 使用基于光门的有源像素传感器的脉冲飞行时间3D-CMOS成像
2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI: 10.1109/ESSCIRC.2009.5325991
Andreas Spickermann, D. Durini, Stefan Brocker, W. Brockherde, B. Hosticka, A. Grabmaier
{"title":"Pulsed time-of-flight 3D-CMOS imaging using photogate-based active pixel sensors","authors":"Andreas Spickermann, D. Durini, Stefan Brocker, W. Brockherde, B. Hosticka, A. Grabmaier","doi":"10.1109/ESSCIRC.2009.5325991","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2009.5325991","url":null,"abstract":"A novel time-of-flight (ToF) 3D-image sensor based on photogate (PG) active pixel structures fabricated in a standard 0.35µm CMOS process is presented. Distance measurements are performed using a pulsed near-infrared (λ=905nm) laser with pulse widths of 30ns to 60ns for distance measurements up to 9m. The developed ToF pixel consists of a photogate (APG=30x30µm2) and four floating diffusion (FD) readout nodes, which enable the detection of reflected laser pulse delay and efficient ambient light suppression. Our fabricated sensor contains 4x16 pixels and exhibits a dynamic range of 56dB and a noise equivalent power of 4.46W/m2 using a single laser pulse.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125405505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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