The impact of semiconductor packaging technologies on system integration an overview

Abstract

We are crossing the threshold of the third revolution in semiconductor packaging. In the '80s, Surface Mount Technology (SMT) had major impact on size reduction of all electronic systems. In the '90s, Ball Grid Array (BGA) has been introduced, whose latest evolution allows further dramatic steps in miniaturization, with cost effective production of 3- dimensional structures and the integration of a large number of passive and active devices in the same package (System in Package - SiP). 3D-BGA platform is now well established and offers an alternative to System on Chip (SoC), i.e. the full integration at chip level. With the additional possibility of combining “heterogeneous” devices [1]. But BGA is getting close to its intrinsic limits and will not be able to serve the requirements (size, speed, thermal dissipation, cost) of next advanced systems, like future wireless applications. At present, most of R&D effort is dedicated to the development of new concepts, mixing conventional assembly and “on wafer” processes. The result is the “3D Wafer Level” platform, which will provide unprecedented levels of integration, with several breakthroughs in design, manufacturing infrastructure, supply chain.