具有1.5周期延迟开销的600MHz电荷恢复FIR滤波器

2009 Proceedings of ESSCIRC Pub Date : 2009-11-10 DOI:10.1109/ESSCIRC.2009.5325975

J. C. Kao, Wei-Hsiang Ma, V. Sathe, M. Papaefthymiou

{"title":"具有1.5周期延迟开销的600MHz电荷恢复FIR滤波器","authors":"J. C. Kao, Wei-Hsiang Ma, V. Sathe, M. Papaefthymiou","doi":"10.1109/ESSCIRC.2009.5325975","DOIUrl":null,"url":null,"abstract":"We present a 14-tap 8-bit FIR chip designed using a novel charge-recovery logic family with only 1.5 cycles of additional latency over the best possible static CMOS design. Fabricated in a 0.13µm CMOS process, the chip operates in the 365—600MHz range with a 3nH on-chip inductor. At its resonant frequency of 466MHz, it dissipates 39.1mW and recovers 45% of the energy supplied to it.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"83 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead\",\"authors\":\"J. C. Kao, Wei-Hsiang Ma, V. Sathe, M. Papaefthymiou\",\"doi\":\"10.1109/ESSCIRC.2009.5325975\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a 14-tap 8-bit FIR chip designed using a novel charge-recovery logic family with only 1.5 cycles of additional latency over the best possible static CMOS design. Fabricated in a 0.13µm CMOS process, the chip operates in the 365—600MHz range with a 3nH on-chip inductor. At its resonant frequency of 466MHz, it dissipates 39.1mW and recovers 45% of the energy supplied to it.\",\"PeriodicalId\":258889,\"journal\":{\"name\":\"2009 Proceedings of ESSCIRC\",\"volume\":\"83 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Proceedings of ESSCIRC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2009.5325975\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Proceedings of ESSCIRC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2009.5325975","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 7

摘要

我们提出了一种14分路8位FIR芯片，采用新颖的电荷恢复逻辑系列设计，与最佳静态CMOS设计相比，仅增加1.5个周期的额外延迟。该芯片采用0.13 μ m CMOS工艺制造，工作频率为365-600MHz，片上电感为3nH。在466MHz谐振频率下，耗散39.1mW，回收供给能量的45%。

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A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead

We present a 14-tap 8-bit FIR chip designed using a novel charge-recovery logic family with only 1.5 cycles of additional latency over the best possible static CMOS design. Fabricated in a 0.13µm CMOS process, the chip operates in the 365—600MHz range with a 3nH on-chip inductor. At its resonant frequency of 466MHz, it dissipates 39.1mW and recovers 45% of the energy supplied to it.

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2009 Proceedings of ESSCIRC

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