{"title":"用于高性能数据流应用的微可编程存储器控制器","authors":"Jérôme Martin, C. Bernard, F. Clermidy, Y. Durand","doi":"10.1109/ESSCIRC.2009.5325981","DOIUrl":null,"url":null,"abstract":"High-performance embedded dataflow systems require intensive data manipulation involving synchronization, buffering, duplication and reordering. Our Microprogrammable Memory Controller (MMC) is designed to handle these tasks more efficiently than the data processing cores. Dataflow management for several computing cores is combined in a single MMC. This reduces the global complexity and memory of the system. The MMC has been implemented in a 65nm low-power CMOS integrated circuit for baseband processing of OFDMA communications. It achieves a bandwidth of 24.6Gbps @385MHz, with an average 38mW power consumption.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"218 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A Microprogrammable Memory Controller for high-performance dataflow applications\",\"authors\":\"Jérôme Martin, C. Bernard, F. Clermidy, Y. Durand\",\"doi\":\"10.1109/ESSCIRC.2009.5325981\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High-performance embedded dataflow systems require intensive data manipulation involving synchronization, buffering, duplication and reordering. Our Microprogrammable Memory Controller (MMC) is designed to handle these tasks more efficiently than the data processing cores. Dataflow management for several computing cores is combined in a single MMC. This reduces the global complexity and memory of the system. The MMC has been implemented in a 65nm low-power CMOS integrated circuit for baseband processing of OFDMA communications. It achieves a bandwidth of 24.6Gbps @385MHz, with an average 38mW power consumption.\",\"PeriodicalId\":258889,\"journal\":{\"name\":\"2009 Proceedings of ESSCIRC\",\"volume\":\"218 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Proceedings of ESSCIRC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2009.5325981\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Proceedings of ESSCIRC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2009.5325981","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Microprogrammable Memory Controller for high-performance dataflow applications
High-performance embedded dataflow systems require intensive data manipulation involving synchronization, buffering, duplication and reordering. Our Microprogrammable Memory Controller (MMC) is designed to handle these tasks more efficiently than the data processing cores. Dataflow management for several computing cores is combined in a single MMC. This reduces the global complexity and memory of the system. The MMC has been implemented in a 65nm low-power CMOS integrated circuit for baseband processing of OFDMA communications. It achieves a bandwidth of 24.6Gbps @385MHz, with an average 38mW power consumption.
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