A 1-V 84-dB DR 1-MHz bandwidth cascade 3–1 Delta-Sigma ADC in 65-nm CMOS

Abstract

This paper presents a switched-capacitor ΔΣ analog-to-digital converter, achieving a dynamic range of 84 dB and a bandwidth of 1 MHz for a power consumption of 17 mW. A cascade 3–1 topology allows aggressive noise-shaping without imposing too stringent specifications on the amplifiers. The design is implemented in a 1 V, 65 nm standard CMOS technology. The use of a novel symmetrical bootstrapped switch solves the non-linearity issues of low-voltage transmission gates. The higher flicker noise of nanoscale CMOS technologies is reduced by applying chopping to the first amplifier input pair.