{"title":"A double balanced power amplifier for S-band phased arrays in SiGe BiCMOS","authors":"H. Erkens, R. Wunderlich, S. Heinen","doi":"10.1109/ESSCIRC.2009.5325990","DOIUrl":null,"url":null,"abstract":"A differential balanced (= ‘double balanced’) power amplifier has been implemented in a 0.25 µm SiGe BiCMOS technology. It delivers most of its maximum output power even with an active load disturbing the PA output with parasitic high power signals. Other features are its excellent output return loss and four point on-chip power generation, decreasing coupling effects. The differential input quadrature splitter and both differential amplifier cores have been integrated on one die measuring 1400 µm x 900 µm. The device has been optimized for operation at S-band (2.9 GHz … 3.1GHz) and reaches a small signal gain of 51 dB with a maximum saturated output power of 24.2 dBm. The double balanced PA withstands active load signals of 18dBm with a low output power penalty of 2.5 dB. Its high tolerance against parasitic element coupling makes the highly integrated device an excellent choice for transmit/receive modules of low-cost commercial phased arrays.","PeriodicalId":258889,"journal":{"name":"2009 Proceedings of ESSCIRC","volume":"66 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Proceedings of ESSCIRC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2009.5325990","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A differential balanced (= ‘double balanced’) power amplifier has been implemented in a 0.25 µm SiGe BiCMOS technology. It delivers most of its maximum output power even with an active load disturbing the PA output with parasitic high power signals. Other features are its excellent output return loss and four point on-chip power generation, decreasing coupling effects. The differential input quadrature splitter and both differential amplifier cores have been integrated on one die measuring 1400 µm x 900 µm. The device has been optimized for operation at S-band (2.9 GHz … 3.1GHz) and reaches a small signal gain of 51 dB with a maximum saturated output power of 24.2 dBm. The double balanced PA withstands active load signals of 18dBm with a low output power penalty of 2.5 dB. Its high tolerance against parasitic element coupling makes the highly integrated device an excellent choice for transmit/receive modules of low-cost commercial phased arrays.