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2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)最新文献

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Nanoscale computing architectures based on resistive switching devices 基于电阻开关器件的纳米级计算架构
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926142
S. Bandyopadhyay, Souradeep Dutta
{"title":"Nanoscale computing architectures based on resistive switching devices","authors":"S. Bandyopadhyay, Souradeep Dutta","doi":"10.1109/ICDCSYST.2014.6926142","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926142","url":null,"abstract":"In this paper we have proposed a new discritized computation scheme, using memristive cross bar array structure. It implements basic logical and arithmetic operation scheme, in the discritized domain. The main advantage of the proposed structures, is the implementation of logical operations in a single step, with minimum complexity. These structures can be implemented in nano scale architectures, and serve as modules in building an ALU.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122983129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA implementation of high speed Vedic multiplier using CSLA for parallel FIR architecture 基于并行FIR架构的CSLA高速吠陀乘法器的FPGA实现
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926136
S. Naaz, M. Pradeep, Satish S. Bhairannawar, Srinivas Halvi
{"title":"FPGA implementation of high speed Vedic multiplier using CSLA for parallel FIR architecture","authors":"S. Naaz, M. Pradeep, Satish S. Bhairannawar, Srinivas Halvi","doi":"10.1109/ICDCSYST.2014.6926136","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926136","url":null,"abstract":"In today's world lots of research work is going in the field of communication and signal processing applications. Every application demands for a higher throughput arithmetic operation. One of the key arithmetic operations is multiplication which takes maximum execution time. The development of efficient multiplier is a subject of interest over decades. So there is a need for an efficient multiplier which obtains higher performance for real time signal processing application. This paper presents the modular design of Vedic multiplier using carry select adder. The delay of proposed multiplier is reduced due to high speed carry select adder. The proposed multiplier is applied to parallel FIR filter. It can be observed that the combinational delay reduced for the proposed multiplier compared to existing architecture.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114815867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Germanium v/s silicon Gate-all-around junctionless nanowire transistor 锗v/s硅栅全无结纳米线晶体管
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926133
Pankaj Kumar, Sangeeta Singh, N. Singh, Bharti Modi, Neelesh Gupta
{"title":"Germanium v/s silicon Gate-all-around junctionless nanowire transistor","authors":"Pankaj Kumar, Sangeeta Singh, N. Singh, Bharti Modi, Neelesh Gupta","doi":"10.1109/ICDCSYST.2014.6926133","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926133","url":null,"abstract":"In this paper, we have analyzed and evaluated Germanium and Silicon Gate-all-around junctionless transistor (GAA-JLT) transistors. We have compared the various analog and digital device performance parameters such as drain current Id, on-current Ion, off-current Ioff, on-current to off current ratio Ion/Ioff, drain induced barrier lower (DIBL), sub-threshold slope (SS), transconductance gm, transgeneration factor (TGF) and cut-off frequency fT are investigated using numerical device simulator 3-D ATLAS version 2.10.18.R. Extensive device simulations show Ge-GAA-JLT transistors has improvement in some dc device performance parameters as compared to Si-GAA-JLT transistors for both digital as well as analog applications. Ge-GAA-JLT shows the major improvement in terms of DIBL, lower threshold voltage and slight decrease in SS also. Hence, Ge-GAA-JLT is found to have improvement in device performance as compared with Si-GAA-JLT.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117037291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High speed low power Full Adder circuit design using current comparison based domino 基于电流比较的高速低功耗全加法器电路设计
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926166
J. Ajayan, D. Nirmal, S. Sivasankari, D. Sivaranjani, M. Manikandan
{"title":"High speed low power Full Adder circuit design using current comparison based domino","authors":"J. Ajayan, D. Nirmal, S. Sivasankari, D. Sivaranjani, M. Manikandan","doi":"10.1109/ICDCSYST.2014.6926166","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926166","url":null,"abstract":"In this paper, a new Full Adder circuit is designed using current comparison based domino logic style, which has a lower leakage and higher noise immunity along with high speed. This circuit achieved high speed and better noise immunity by reducing the parasitic capacitance on the dynamic node, yielding a keeper in the pull up network. The leakage current is reduced by introducing a transistor in diode configuration. The full adder circuit is simulated in 0.12μm CMOS technology with VDD =1.2V. The total average power dissipation is 24μw at temperature T=120°C with a layout area of 116μm2The total capacitance at the dynamic node is computed as 8fF from the layout and this capacitance includes all the parasitic capacitances associated with the dynamic node.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132019851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of positive & negative edge triggered D-flip flop using AlGaAs/GaAs MODFET technology 利用AlGaAs/GaAs MODFET技术设计正负边触发d触发器
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926217
V. Ganesan, K. S. Shaji
{"title":"Design of positive & negative edge triggered D-flip flop using AlGaAs/GaAs MODFET technology","authors":"V. Ganesan, K. S. Shaji","doi":"10.1109/ICDCSYST.2014.6926217","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926217","url":null,"abstract":"This paper enumerates the design of high speed Positive & Negative edge triggered D flip flops using AlGaAs/GaAs MODFET. This Flip Flops having less number of transistors. It can be efficiently used in VLSI ICs. The verification is done using simulation the proposed Flip Flops appear to have better speed of operation. It is simple and suitable to SPICE simulation of hybrid digital ICs.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134209242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Residue arithmetic's using reversible logic gates 使用可逆逻辑门的残数算法
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926193
I. B. K. Raju, P. Kumar, P. Rao
{"title":"Residue arithmetic's using reversible logic gates","authors":"I. B. K. Raju, P. Kumar, P. Rao","doi":"10.1109/ICDCSYST.2014.6926193","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926193","url":null,"abstract":"The Residue number system (RNS) has been employed for efficient parallel carry-free arithmetic computations in DSP applications. Residue addition is the instrumental component in implementing residue converters and channels in RNS. On the other side Reversible Logic is becoming one of the potential power optimization techniques in Low Power CMOS design. In this research paper we have proposed CMOS implementation of two different reversible logic architectures for 4-bit generic modulo-m ripple residue adder using 4×4 TSG, DPG and 3×3 Fredkin Reversible logic gates and one architecture for 4-bit generic modulo-m carry look ahead residue adder using 4×4 RMF and 3×3 Fredkin Reversible logic gates along with two irreversible logic based 4-bit generic modulo-m residue adder one for irreversible 4-bit generic modulo-m ripple residue adder and another for 4-bit generic modulo-m carry look ahead adder. Proposed architectures are analyzed in terms of power, delay, garbage o/p, constant inputs and transistor count using 180nm technology node at 1.8 v with operating frequency of 200 MHz. It is observed that DPG based Reversible Residue Ripple adder has 40% more efficient than irreversible Residue Ripple adder and RMF based Reversible Residue CLA adder has 33% more efficient than irreversible Residue CLA added. The implementation is based on Reversible pass transistor Logic (R-CPL).","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133596160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Preparation and characterization of LiNbO3 thin films by the aqueous citric gel method 柠檬酸凝胶法制备LiNbO3薄膜及表征
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926186
B. Sivakumar, S. Gokul Rai, G. Ramesh Kumar
{"title":"Preparation and characterization of LiNbO3 thin films by the aqueous citric gel method","authors":"B. Sivakumar, S. Gokul Rai, G. Ramesh Kumar","doi":"10.1109/ICDCSYST.2014.6926186","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926186","url":null,"abstract":"LiNbO3 thin films with well-developed grains were fabricated by spin-coating on SiO2(111) substrates. Annealing in static air and oxygen atmosphere was performed at 400° C 500° C 600° C for 3 h. The films obtained were characterized by thin film XRD, scanning electron microscopy and elemental analysis. Electrical characterizations of the films pointed to ferroelectricity via hysteresis loop. The influence of oxygen atmosphere on crystallization, morphology and properties of LiNbO3 thin films is discussed.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129028630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA implementation of secure image compression with 2D-DCT using Verilog HDL 基于Verilog HDL的2D-DCT安全图像压缩FPGA实现
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926210
B. Jeevan, C. N. Bhatt, C. V. Krishna, K. Sivani
{"title":"FPGA implementation of secure image compression with 2D-DCT using Verilog HDL","authors":"B. Jeevan, C. N. Bhatt, C. V. Krishna, K. Sivani","doi":"10.1109/ICDCSYST.2014.6926210","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926210","url":null,"abstract":"The Secure Image Compression consists of JPEG encoder in which 2D-DCT (2Dimensional - Discrete Cosine Transform) is used to provide security while compressing the image. In this paper Verilog design and hardware implementation of pipelined 2-D DCT are described. The architecture uses 4327 slices, 7621 LUTs, 25 I/Os of FPGA Spartan3E-XC3S500E and works at an operating frequency of 89.469MHz. The delay of processing each 8*8 block in an image is evaluated to be 9.167ns and pipeline latency is 66 clock cycles.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116295326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Effects of Germanium mole fraction variation at the source of a dielectrically modulated Tunneling FET based biosensor 介电调制隧道效应场效应管生物传感器源锗摩尔分数变化的影响
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926218
S. Kanungo, P. Gupta, Hafizur Rhaman
{"title":"Effects of Germanium mole fraction variation at the source of a dielectrically modulated Tunneling FET based biosensor","authors":"S. Kanungo, P. Gupta, Hafizur Rhaman","doi":"10.1109/ICDCSYST.2014.6926218","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926218","url":null,"abstract":"In this work, the effect of Germanium mole fraction variation in the source region of a dielectrically modulated Silicon Tunneling Field Effect Transistor (DMTFET) based biosensor has been investigated with the help of extensive device-level simulation. Results show that the increasing germanium mole fraction significantly reduces the DMTFET sensitivity towards the bio-molecules, and the degree of this sensitivity degradation has strong dependence on the properties of bio-molecule namely dielectric constant and charge density. The increasing Germanium mole fraction reduces the effect of gate fringing field at the source region and consequently the conduction band lowering being diminished in this region, resulting in the sensitivity degradation in the DMTFET biosensor. This study offers a fair design level understanding over the use of Silicon-Germanium source in DMTFET based biosensor.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124766797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm 采用20nm异质结隧道效应设计高能效逻辑门
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926177
Harshita Vallabhaneni, A. Japa, Sadulla Shaik, K. Rama Krishna, R. Vaddi
{"title":"Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm","authors":"Harshita Vallabhaneni, A. Japa, Sadulla Shaik, K. Rama Krishna, R. Vaddi","doi":"10.1109/ICDCSYST.2014.6926177","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926177","url":null,"abstract":"This paper presents the design insights and benchmarking of 20nm Hetero-junction Tunnel transistor (HTFET) as steep slope device for designing energy efficient logic gates. 20nm Si FinFET technology has been used for benchmarking HTFET circuit performance. The HTFET logic topologies have improved robustness and energy efficiency over Si FinFET topology, particularly for small supply voltages. This work further explores the analysis of HTFET based cascaded chain of inverters to drive a large capacitive load. It has been demonstrated that HTFET based circuit design opens path for energy efficient logic design not achievable with CMOS technology at small supply voltages.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122469848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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