Diptendu Kumar Kundu, S. Srimani, Saradindu Panda, B. Maji
{"title":"Implementation of optimized high performance 4×4 multiplier using ancient Vedic sutra in 45 nm technology","authors":"Diptendu Kumar Kundu, S. Srimani, Saradindu Panda, B. Maji","doi":"10.1109/ICDCSYST.2014.6926192","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926192","url":null,"abstract":"With the enrichment of new technology in the fields of VLSI design and communication there is also a demand of high speed and low area. The aim of this paper is to design a multiplier circuit based on Vedic sutras. The algorithms based on conventional mathematics can be optimized and simplified by using Vedic sutras. In this paper we have given the design up to Multipliers based on Vedic multiplication sutra “Urdhva-Tiryakbhyam” the design of 2×2, 4×4 has been designed in DSCH2 and all the outputs have been given. The layout of those circuits has been also generated by Microwind. The internal circuit diagram of all the blocks has been explained The noise, power have been calculated by T-Spice-13 in 45nm Technology. The hardware has also been implemented in XILINX and tested in Basys™2 Spartan-3E FPGA Board.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132977547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Folded FFT architecture for real-valued signals based on Radix-23 algorithm","authors":"P. Zode, Abhilesh S. Thor, A. Deshmukh","doi":"10.1109/ICDCSYST.2014.6926178","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926178","url":null,"abstract":"A new FFT architecture for real-valued signal is proposed using Radix-23 algorithm. It is based on modifying flow graph of the FFT algorithm such that it has both real and complex datapaths. A redundant operation in flow graph is replaced by imaginary part. Using folding technique RFFT architecture with any level of parallelism can be achieved. This RFFT architecture will lead to low hardware complexity as compare to radix-2 and radix 22 algorithm in terms of adder, multiplier and delay. N-point 2 parallel radix-23 architecture requires (log8N-) complex multiplier, 2log2N adders, 3N/2-2 delays. RFFT which is used for real time applications and in portable devices for which low power consumption is main requirement, so accordingly carry propagate adder which has least power consumption and CSD multiplier is selected for our proposed architecture.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124122931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FPGA implementation of synchronous section-carry based carry look-ahead adders","authors":"K. Preethi, P. Balasubramanian","doi":"10.1109/ICDCSYST.2014.6926150","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926150","url":null,"abstract":"It is common knowledge that carry look-ahead adders constitute a high-speed method of performing binary addition in logarithmic time. As an improvement, in this paper, FPGA based realization of high-speed carry look-ahead adders based on the concept of section-carry is discussed. Three kinds of carry look-ahead adder architectures viz. Type 1, Type 2, Mixed are presented. In comparison with conventional carry look-ahead adders of sizes 16, 32 and 64-bits, the proposed section-carry based carry look-ahead adders report improvements in speed of 14.9%, 12.1% and 13% for Type 1, Type 2 and Mixed topologies respectively, for simulations targeting a 90nm FPGA device.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115266821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance analysis of energy aware routing protocol for Wireless Sensor Networks","authors":"Pramod Kumar, A. Chaturvedi","doi":"10.1109/ICDCSYST.2014.6926168","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926168","url":null,"abstract":"The main issues in wireless Sensor Networks (WSNs) are efficient uses of limited resources and appropriate routing of network path. To overcome these issues multiple sinks are most efficient and effective with proper routing protocols. The residual energy status of entire network nodes of single stationary and multiple sink are compared with number of queries supported and its performances are also evaluated.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115289496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"VLSI (FPGA) design for distinctive division architecture using the Vedic sutra ‘Dhwajam’","authors":"S. Oke, Suraj Lulla, Prathamesh Lad","doi":"10.1109/ICDCSYST.2014.6926137","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926137","url":null,"abstract":"In this paper we have discussed the VLSI implementation of a unique division architecture using a method known as the `Dhwajam', a novel method, from the annals of Vedic Mathematics. Vedic Mathematics is an antediluvian branch of Indian mathematics with sixteen special formulae. The `Dhwajam', also known as the flag method, shows exceptionally low computational complexity as described. The `Dhwajam' is unique in a way that it can be generalized, be exploited to the fullest with large scale implementation and has not been explored before. Its inherent parallelism too is much suitable for VLSI implementation. The division scheme was implemented in Xilinx 8.1 ISE and results were tested on spartan3 FPGA platform.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125264194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"TCAD assessment of dual material gate nanoscale RingFET (DMG-RingFET) for analog and digital applications","authors":"Sachin Kumar, V. Kumari, Mridula Gupta, M. Saxena","doi":"10.1109/ICDCSYST.2014.6926181","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926181","url":null,"abstract":"In this work, the impact of gate material engineering on the performance of RingFET architecture i.e. Dual Material Gate RingFET (DMG-RingFET) has been investigated for the first time using ATLAS 3D device simulation. A fair comparison has also been drawn between the performance of DMG-RingFET and SMG RingFET device architectures. The impact of high-k gate dielectric on the performance of DMG RingFET has also been presented. Various important analog and digital performance metrics such as drain current (Ids), transconductance (gm), transconductance generation efficiency (gm/Ids), early voltage (Vea), output voltage of inverter and inverter gain has been discussed in detail. In addition to this investigation of DMG-RingFET as an inverter has been performed to demonstrate the reliability of DMG-RingFET architecture for digital circuit application.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116413911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Bhowmick, S. Baishya, R. Goswami, B. Dasv, C. Joishy
{"title":"An optimized SOI g-TFET and its application in a half adder circuit","authors":"B. Bhowmick, S. Baishya, R. Goswami, B. Dasv, C. Joishy","doi":"10.1109/ICDCSYST.2014.6926156","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926156","url":null,"abstract":"In this paper, gate induced band-to-band tunneling transistors are explored as a low voltage alternative because of their potential to achieve lower than 60mV/decade turn-off. Since BTBT is strongly dependant on the band gap of the semiconductor, lower band gap materials can help scaling down of Vnn-By engineering the transistor device structure and gate, such that the onset of tunneling occurs in a region of high electric field, results in steep sub 60 mY/dec response over many decades of current. The proposed SOI g-TFET design utilizes heavily doped pocket, ultra shallow N+/P+ junctions to achieve sudden tunneling. In simulation results it is shown that Vnn down to sub 500 mV is possible if suitable low-Eg material like Si-Ge is introduced. Non local tunneling probability is considered and drain current is found to be proportional to the same. The proposed device is utilized in the analysis of a half adder due to its advantages over the conventional ones.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114490459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance analysis of mixed integer linear programming with wavelength division multiplexing","authors":"R. Vinolee, V. Bhaskar","doi":"10.1109/ICDCSYST.2014.6926153","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926153","url":null,"abstract":"Wavelength division multiplexing network is a method to improve capacity of transmission and to design the best path between the source and destination and assign the wavelength to the path for data transmission. A simple node is to be designed with Mixed Integer Linear Programming /GPLK 4.4 as the mathematical problem formulation for the single-hop and virtual hop of the network. Comparison of the topologies, INTERNET, EON and National Science Foundation Network (NSFNET) With Wavelength Division Multiplexing Conversion having different light-path flows is made for different number of nodes with capacity and average Ingress, Egress and groomed traffic. The performance metrics is determined by Wavelength of Light paths, single hop path, Number of Virtual hops, Network Congestion, Number of Wavelength per link, and Wavelength channel capacity.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123831277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Data security using serial commutative RSA CORE for multiple FPGA system","authors":"R. Ambika, S. Ramachandran, K. R. Kashwan","doi":"10.1109/ICDCSYST.2014.6926198","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926198","url":null,"abstract":"Security systems play a vital role in protecting the important data in the organizations or multiple transceiver based communication systems and cryptography is one of the primary ways to protect the data. RSA algorithm is extensively used in the popular implementations of Public Key Infrastructures. Many cryptographic protocols and attacks on these protocols make use of the fact that the order in which encryption is performed does not affect the result of the encryption, i.e., encryption is commutative. This paper presents the implementation of a cryptography core based on Commutative RSA public key cryptography algorithm for accomplishing data security and authentication in environment comprising multiple FPGA cores without any key exchange overheads. In this work, in spite of considering conventional two terminal communications, we have implemented a scalable architecture for multi distributed FPGA based systems that realizes commutative RSA algorithm for verifying data security among multiple transceiver terminals. The proposed system architecture has used the Montgomery multiplication algorithm with exponential modular multiplication and Radix-2 multiplication based multiparty cryptography. The proposed multiplier is able to work with any precision of the input operands, limited only by memory or control constraints. The result obtained for this approach has illustrated a very high computational efficiency with minimum memory or space occupancy and higher operational frequency.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124210421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of adaptive filter for channel estimation","authors":"D. Bhoyar, C. Dethe, M. Mushrif","doi":"10.1109/ICDCSYST.2014.6926173","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926173","url":null,"abstract":"Adaptive Channel Estimator is a most important research topic in wireless communication. Here we have to reduce the error from the received signal which may be corrupted by the environmental reason or due to the multipath fading. In this paper we are concentrated more on the hardware implementation of Adaptive filter using LMS algorithm which has been synthesized within FPGA. In this paper our main aim is to implement the LMS core in FPGA by using VHDL code and observe its synthesis and simulation result.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126486953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}