2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)最新文献

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Contour-contrast enhancement based on retinal layer processing 基于视网膜层处理的轮廓对比度增强
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926162
T. Rajalakshmi, S. Prince
{"title":"Contour-contrast enhancement based on retinal layer processing","authors":"T. Rajalakshmi, S. Prince","doi":"10.1109/ICDCSYST.2014.6926162","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926162","url":null,"abstract":"The Human Visual System (HVS) model based image quality metrics, correlates strongly with the evaluations of image quality as well as with human observer performance in visual recognition process. Physiological modeling of retina plays a vital role in the development of high performance image processing methods to produce better visual perception. The retina is a complex neural structure, which does not only detect an incoming light signal, but also proceeds to many complex signal transformations. The retina is a laminated structure consisting of alternating layers of cell bodies and cell processes. The main aim of this work is to develop a model of photoreceptor and outer plexiform layer considering the properties of compression and spatiotemporal filtering in the processing of visual information. In this work spatial frequency value is evaluated using Discrete cosine Transform (DCT) technique thereby enhancing the contrast visibility in dark area and maintaining the same in bright area using photoreceptor layer of retina and a model to enhance contour contrast is developed using outer plexiform layer of retina.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115570632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Advantage of CNTFET characteristics over MOSFET to reduce leakage power CNTFET特性优于MOSFET,可降低泄漏功率
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926211
S. K. Sinha, S. Chaudhury
{"title":"Advantage of CNTFET characteristics over MOSFET to reduce leakage power","authors":"S. K. Sinha, S. Chaudhury","doi":"10.1109/ICDCSYST.2014.6926211","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926211","url":null,"abstract":"In this paper we compare and justify the advantage of CNTFET devices over MOSFET devices in nanometer regime. Thereafter we have analyzed the effect of chiral vector, and temperature on threshold voltage of CNTFET device. After simulation on HSPICE tool we observed that the high threshold voltage can be achieved at low chiral vector pair. It is also observed that the effect of temperature on threshold voltage of CNTFET is negligibly small. After analysis of channel length variation and their impact on threshold voltage of CNTFET as well as MOSFET devices, we found an anomalous result that the threshold voltage increases with decreasing channel length in CNTFET devices, this is quite contrary to the well known short channel effect. It is observed that at below 10 nm channel length the threshold voltage is increased rapidly in case of CNTFET device whereas in case of MOSFET device the threshold voltage decreases drastically below 10 nm channel length.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114301991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Torque ripple minimization & closed loop speed control of BLDC motor with hysteresis current controller 带磁滞电流控制器的无刷直流电动机转矩脉动最小化及闭环速度控制
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926122
J. E. Muralidhar, P. V. Aranasi
{"title":"Torque ripple minimization & closed loop speed control of BLDC motor with hysteresis current controller","authors":"J. E. Muralidhar, P. V. Aranasi","doi":"10.1109/ICDCSYST.2014.6926122","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926122","url":null,"abstract":"In Brushless DC (BLDC) motor ripple-free torque can be produced by preshaping the excitation currents with the help of electronically controlled commutators. This ripple-free torque minimizes copperlosses. In this paper, the position-sensorless direct torque and indirect flux control of brushless dc (BLDC) motor with non sinusoidal back electromotive force (EMF) has been extensively proposed. In the literature, several methods have been proposed for BLDC motor drives to obtain optimum current and to obtain optimum current and torque control pulsations in BLDC motor drives. Most methods are complicated and do not consider the stator flux linkage control, therefore, possible high-speed operations are not feasible. In this study, a novel and simple approach to achieve a low-frequency torque ripple-free direct control with maximum efficiency is presented. This method does not require pulse width modulation and need proportional plus integral regulator with respective hysteresis current controlling technique and also permits the regulation of varying signals. The validity and practical applications of the proposed sensorless three-phase BLDC motor drive scheme are verified through simulations results using Matlab/Simulink Platform.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"522 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123573318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Efficient hardware implementation of scalable FFT using configurable Radix-4/2 使用可配置的Radix-4/2的可扩展FFT的高效硬件实现
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926131
S. Ranganathan, R. Krishnan, H. Sriharsha
{"title":"Efficient hardware implementation of scalable FFT using configurable Radix-4/2","authors":"S. Ranganathan, R. Krishnan, H. Sriharsha","doi":"10.1109/ICDCSYST.2014.6926131","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926131","url":null,"abstract":"This paper demonstrates the FPGA implementation of FFT algorithm that is precisely designed to induce an efficient implementation of the parameters involving area and performance by configuring the size of FFT input points which is well suited for wireless and signal processing applications. An optimized architecture is demonstrated in this paper for computing FFT of length 8/16/32/64/128/512 and 1024 using Radix-4/Radix 2*2 FFT in FPGA and is compared with Xilinx LogiCore™ FFT IP with configurable point size. It is found that proposed design is more efficient and effective in terms of area and performance while achieving the input system configurability. A novel Address Generator architecture has been proposed which facilitates for Complex Math Processor (CMP). This single generator helps in effectively carrying out the address mapping scheme. The occurrence of hardware overheads is minimized by using the multiplexor for complex arithmetic's. The entire RTL design is described using Verilog HDL and simulated using Xilinx ISim. This experimental result is tested on Spartan-6 XC6SLX4, which is the smallest device on Spartan 6 family and found that Xilinx FFT IP core over maps the available DSP48 slices. The result shows 538 LUT's, 847 Flip Flops, 3 DSP Slices, Maximum Frequency of 217 MHz. This is about 60% improvement in resource usage and 14% upgrade in the performance thus creating a low cost Configurable FFT Processor.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130310376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Providing reliability using potent features of iris recognition 利用虹膜识别的有效特征提供可靠性
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926146
Shreyas Pathak, S. Zafar
{"title":"Providing reliability using potent features of iris recognition","authors":"Shreyas Pathak, S. Zafar","doi":"10.1109/ICDCSYST.2014.6926146","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926146","url":null,"abstract":"Aren't you love to substitute password based entry control to avoid having to reset forgotten password and worry about the integrity of your system? Aren't you cognate to rest secure in comfort that your healthcare system does not solely on your social security number as proof of your identity for granting access to your medical records? As a result each of these questions are seemly more and more serious, access to a reliable personal identification is becoming enlarging essential, Traditional method of identification based on occupancy of ID cards or exclusive knowledge like a social security number or a password are not all together reliable. ID cards can be lost forged or misplaced; passwords can be forgotten or compromised. But an iris is apparently connected to its owner. It can no more be borrowed stolen or easily forged. Iris recognition technology may solve this problem since a iris is undeniably connected to its owner. It's nontransferable. The system can then compare scans to records stored in a central or local database or even on a smart card. We propose a model and an algorithm for better bidding of resources, improving the run time and handover reliability to the user.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129911656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A neural network based approach to predict high voltage li-ion battery cathode materials 基于神经网络的高压锂离子电池正极材料预测方法
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926140
Tanmay Sarkar, Alind Sharma, A. Das, Dipti Deodhare, M. Bharadwaj
{"title":"A neural network based approach to predict high voltage li-ion battery cathode materials","authors":"Tanmay Sarkar, Alind Sharma, A. Das, Dipti Deodhare, M. Bharadwaj","doi":"10.1109/ICDCSYST.2014.6926140","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926140","url":null,"abstract":"This paper introduces the concept of using Artificial Neural Network (ANN) techniques for predicting electrochemical potential of cathode materials in combination with first-principles based quantum mechanical calculations. The proposed method can be used to predict the Lithium ion battery voltage if a new material is chosen as cathode. The methodology has low time-space complexity of computation and aims to integrate ANN with quantum mechanics based Density Functional Theory (DFT) calculations for accelerated insertion of new materials into engineering systems. It can be helpful in establishing new structure property correlations among large, heterogeneous and distributed data sets. ANN based modelling opens up the opportunity of screening large number of lithium based compositions for identifying promising materials within limited time and computational resources and can be further extended to all other battery materials.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131203968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Analytical modeling of a split-gate dielectric modulated metal-oxide-semiconductor field-effect transistor for application as a biosensor 用于生物传感器的分栅介质调制金属-氧化物半导体场效应晶体管的分析建模
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926183
Ajay, R. Narang, M. Saxena, Mridula Gupta
{"title":"Analytical modeling of a split-gate dielectric modulated metal-oxide-semiconductor field-effect transistor for application as a biosensor","authors":"Ajay, R. Narang, M. Saxena, Mridula Gupta","doi":"10.1109/ICDCSYST.2014.6926183","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926183","url":null,"abstract":"In this paper, an analytical model of a split-gate dielectric modulated Metal-oxide-semiconductor field-effect transistor (DM-MOSFET) for label free electrical detection of the biomolecules has been proposed. To provide a binding site for the biomolecules the channel region of MOSFET is left open in the four-gate configuration which is conventionally covered by the gate electrode. As result, the surface potential in this open area is affected by the neutral and charged biomolecules that binds to the underlap (open) channel. The solution of surface potential is obtained by solving a 2-D Poisson equation assuming parabolic potential profile along the channel direction using conformal mapping technique. The analytical model of threshold voltage is derived from the surface potential model and change in the threshold voltage is used as a sensing metric for detection of biomolecules after immobilization in the open region. The characteristics trends are supported and verified via “ATLAS” device simulation software.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126258288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An efficient new hybrid cascaded H-bridge inverter for photovoltaic system 一种高效的新型混合级联h桥逆变器
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926206
S. Selvakumar, A. Vinothkumar, M. Vigneshkumar
{"title":"An efficient new hybrid cascaded H-bridge inverter for photovoltaic system","authors":"S. Selvakumar, A. Vinothkumar, M. Vigneshkumar","doi":"10.1109/ICDCSYST.2014.6926206","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926206","url":null,"abstract":"This paper deals with electricity from photovoltaic system for cascaded multilevel inverter. The general function of multilevel inverter is to synthesis desired voltage from solar source. This inverter has advantageous of industrial applications. The use of converters will increase losses and cost in conventional methods. The proposed nine level multilevel inverter with solar energy using Pulse Width Modulation Technique (PWM) of providing high switching frequency will highly reduce harmonics.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126514748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Attribute based encryption for securing personal health record on cloud 基于属性的加密,用于保护云上的个人健康记录
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926174
Deepali A. Gondkar, V. Kadam
{"title":"Attribute based encryption for securing personal health record on cloud","authors":"Deepali A. Gondkar, V. Kadam","doi":"10.1109/ICDCSYST.2014.6926174","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926174","url":null,"abstract":"Personal health record (PHR) has emerged as a patient-centric model of health information exchange. A PHR service allows a patient to create, manage, and control her personal health data in one place through the web, which has made the storage, retrieval, and sharing of the medical information more efficient. Especially, each patient is promised the full control of her medical records and can share her health data with a wide range of users, including healthcare providers, family members or friends. The main aim of this research work is to propose a novel framework of secure sharing of personal health records in cloud computing. Considering partially trustworthy cloud servers, we argue that to fully realize the patient-centric concept, patients shall have complete control of their own privacy through encrypting their PHR files to allow fine-grained access.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125510473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Performance assessment of different Network-on-Chip topologies 不同片上网络拓扑的性能评估
2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926188
Tetala Neel Kamal Reddy, A. Swain, J. Singh, K. Mahapatra
{"title":"Performance assessment of different Network-on-Chip topologies","authors":"Tetala Neel Kamal Reddy, A. Swain, J. Singh, K. Mahapatra","doi":"10.1109/ICDCSYST.2014.6926188","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926188","url":null,"abstract":"Multiprocessor System-on-Chip platforms are gaining prominence in the field of SoC design, which accommodates several large heterogeneous semiconductor intellectual property (IP) blocks, integrated onto a single chip. However, there's a crisis of global interconnection with existing bus architectures in such SoC Designs. In response to this crisis, Network-on-Chip (NoC) is an upcoming paradigm, and is becoming the leading contender to replace the conventional bus architectures. Many Network-on-Chip topologies have been proposed in an attempt to tackle various chip architecture needs and routing techniques. In this paper, some of the topologies such as Mesh, Torus, Binary Tree and Butterfly Fat Tree (BFT) have been simulated using a Network Simulator (NS2) and their performances have been assessed and compared taking throughput, maximum end-to-end latency and dropping probability as assessment parameters.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124659777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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