2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)最新文献_第9页

RF and microwave characteristics of a 20nm gate length InAlN/GaN-based HEMT having a high “Figure of Merit” 具有高“品质系数”的20nm栅长InAlN/ gan基HEMT的射频和微波特性

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926151

A. Bhattacharjee, T. Lenka

引用次数: 0

Improved fused floating point add-subtract and multiply-add unit for FFT implementation 改进的FFT实现的融合浮点加减和乘加单元

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926157

P. Palsodkar, A. Gurjar

引用次数: 7

FPGA based realization of OFDM transceiver system for Software Defined Radio 基于FPGA的软件无线电OFDM收发系统实现

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926167

Neenu Joseph, P. Kumar

引用次数: 4

A clustering based hybrid routing protocol for enhancing network lifetime of Wireless Sensor Network 一种提高无线传感器网络生存期的基于聚类的混合路由协议

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926119

J. Gnanambigai, N. Rengarajan, N. Navaladi

引用次数: 13

A review on feature extraction and denoising of ECG signal using wavelet transform 基于小波变换的心电信号特征提取与去噪研究进展

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926190

V. Seena, Jerrin Yomas

{"title":"A review on feature extraction and denoising of ECG signal using wavelet transform","authors":"V. Seena, Jerrin Yomas","doi":"10.1109/ICDCSYST.2014.6926190","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926190","url":null,"abstract":"The electrocardiogram is a technique of recording bioelectric currents generated by the heart which is useful for diagnosing many cardiac diseases. The feature extraction and denoising of ECG are highly useful in cardiology. Wavelet based methods present best performance as irregularity measures and makes them suitable for ECG data analysis. This paper proposes comparison of different feature extraction and denoising techniques using wavelet transform. In an ECG with P-QRS-T wave, QRS complex has the most striking part for analysis. The first part of the paper deals with comparison of three different feature extraction techniques using wavelet transform. The second part deals with the denoising of ECG signal using three different wavelet transform. The most troublesome noise sources contain frequency components within ECG spectrum, i.e. electrical activity of the muscles and instability of electrode skin contact. Such noises are difficult to remove using typical filter procedure. In such cases signal noise reduction is only possible with wavelet denoising techniques. The comparison of different wavelet transform techniques for feature extraction and denoising of ECG signal is mentioned, which is suitable for the selection of most applicable techniques. Wavelet transform is a powerful tool for the analysis of ECG signal.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128119166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 64

Power, delay and noise margin comparison of binary and quaternary SRAM 二进制和四元SRAM的功率、延迟和噪声裕度比较

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926172

D. Borkute, Pratibha Patel, P. Dakhole

{"title":"Power, delay and noise margin comparison of binary and quaternary SRAM","authors":"D. Borkute, Pratibha Patel, P. Dakhole","doi":"10.1109/ICDCSYST.2014.6926172","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926172","url":null,"abstract":"The explosive growth of semiconductor industry over a decade have been driven by rapid scaling of complementary metal-oxide-semiconductor (CMOS) technology. Multiple-valued logic allows the reduction of the required number of signals in the circuit, so can be effectively used to reduce the impact of interconnections [12]. In addition to the reduction in interconnections, multiple-valued logic also offers a possibility of increasing the functional complexity, producing circuits that have performance comparable to the binary circuits. Memory application is an area where the multi-valued approach has been successfully used to design commercial integrated circuits. Memories are designed with objective to reduce area, while maintaining proper timing characteristics. This paper presents a comparative study of delay and power consumption of binary and quaternary circuit implementations of SRAM. Larger number of logic functions can be accommodate in quaternary circuits decreasing the number of data interconnect lines and processing components and logic circuits can represent numbers with fewer bits than binary. Static Noise Margin (SNM) is the most important parameter for memory design, affecting both read and write margin [8]. Both cell ratio and pull-up ratio are important parameters because these are the only parameters in the hand of the design engineer, static noise margin of the SRAM cell depends on the cell ratio (CR), supply voltage and also pull up ratio [8]. We have also found bit rate of both circuits for comparative study.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128135986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Low power and high speed level shifters in 0.18um technology 采用0.18um技术的低功耗和高速电平移位器

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926214

O. Kumar, D. Moni, F. Princess

引用次数: 0

A comprehensive analysis of SOI-TFET with novel AlxGa1−xAs channel material 新型AlxGa1−xAs通道材料SOI-TFET的综合分析

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926155

S. Chander, S. Baishya

引用次数: 1

Analysing and improving the performance of software code for Real Time Embedded systems 实时嵌入式系统软件代码的性能分析与改进

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926134

Prashant V. Joshi, K. Gurumurthy

{"title":"Analysing and improving the performance of software code for Real Time Embedded systems","authors":"Prashant V. Joshi, K. Gurumurthy","doi":"10.1109/ICDCSYST.2014.6926134","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926134","url":null,"abstract":"Real Time Embedded systems are characterized by the presence of a processor, on which application specific programs have to run. These application specific dedicated programs are called “Embedded Software or Firmware”. Since most of the activity of the processor is controlled by the software, its efficient design plays a key role in the system design. Efficient software or firmware programming also leads to high performance embedded systems. Also in the present scenario ARM based processors are most widely accepted for higher end applications. Hence in this paper we mainly focus on the analysis and optimization of the Embedded software code running on ARM processors. Various techniques like data dependency, loop optimization, etc., are investigated and studied to enhance the performance of the software in terms of code density, speed of operation, both at high level (Embedded-C) and at the assembly level. Comparing the obtained results with the works in the literature, shows an improvement of 40% with respect to the code density and by 30% in the speed of operation. Further efficient embedded firmware like linear convolution and LCD module are designed by using various optimization techniques. All the simulations are carried out using the IAR workbench.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134399674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Implications of transport models on the analog performance of Gate Electrode Workfunction Engineered (GEWE) Silicon Nanowire MOSFET 传输模型对栅极工作函数工程(GEWE)硅纳米线MOSFET模拟性能的影响

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926154

N. Gupta, R. Chaujar

引用次数: 10