Efficient hardware implementation of scalable FFT using configurable Radix-4/2

This paper demonstrates the FPGA implementation of FFT algorithm that is precisely designed to induce an efficient implementation of the parameters involving area and performance by configuring the size of FFT input points which is well suited for wireless and signal processing applications. An optimized architecture is demonstrated in this paper for computing FFT of length 8/16/32/64/128/512 and 1024 using Radix-4/Radix 2*2 FFT in FPGA and is compared with Xilinx LogiCore™ FFT IP with configurable point size. It is found that proposed design is more efficient and effective in terms of area and performance while achieving the input system configurability. A novel Address Generator architecture has been proposed which facilitates for Complex Math Processor (CMP). This single generator helps in effectively carrying out the address mapping scheme. The occurrence of hardware overheads is minimized by using the multiplexor for complex arithmetic's. The entire RTL design is described using Verilog HDL and simulated using Xilinx ISim. This experimental result is tested on Spartan-6 XC6SLX4, which is the smallest device on Spartan 6 family and found that Xilinx FFT IP core over maps the available DSP48 slices. The result shows 538 LUT's, 847 Flip Flops, 3 DSP Slices, Maximum Frequency of 217 MHz. This is about 60% improvement in resource usage and 14% upgrade in the performance thus creating a low cost Configurable FFT Processor.