Folded FFT architecture for real-valued signals based on Radix-23 algorithm

Abstract

A new FFT architecture for real-valued signal is proposed using Radix-23 algorithm. It is based on modifying flow graph of the FFT algorithm such that it has both real and complex datapaths. A redundant operation in flow graph is replaced by imaginary part. Using folding technique RFFT architecture with any level of parallelism can be achieved. This RFFT architecture will lead to low hardware complexity as compare to radix-2 and radix 22 algorithm in terms of adder, multiplier and delay. N-point 2 parallel radix-23 architecture requires (log8N-) complex multiplier, 2log2N adders, 3N/2-2 delays. RFFT which is used for real time applications and in portable devices for which low power consumption is main requirement, so accordingly carry propagate adder which has least power consumption and CSD multiplier is selected for our proposed architecture.