An optimized SOI g-TFET and its application in a half adder circuit

Abstract

In this paper, gate induced band-to-band tunneling transistors are explored as a low voltage alternative because of their potential to achieve lower than 60mV/decade turn-off. Since BTBT is strongly dependant on the band gap of the semiconductor, lower band gap materials can help scaling down of Vnn-By engineering the transistor device structure and gate, such that the onset of tunneling occurs in a region of high electric field, results in steep sub 60 mY/dec response over many decades of current. The proposed SOI g-TFET design utilizes heavily doped pocket, ultra shallow N+/P+ junctions to achieve sudden tunneling. In simulation results it is shown that Vnn down to sub 500 mV is possible if suitable low-Eg material like Si-Ge is introduced. Non local tunneling probability is considered and drain current is found to be proportional to the same. The proposed device is utilized in the analysis of a half adder due to its advantages over the conventional ones.