FPGA implementation of secure image compression with 2D-DCT using Verilog HDL

Abstract

The Secure Image Compression consists of JPEG encoder in which 2D-DCT (2Dimensional - Discrete Cosine Transform) is used to provide security while compressing the image. In this paper Verilog design and hardware implementation of pipelined 2-D DCT are described. The architecture uses 4327 slices, 7621 LUTs, 25 I/Os of FPGA Spartan3E-XC3S500E and works at an operating frequency of 89.469MHz. The delay of processing each 8*8 block in an image is evaluated to be 9.167ns and pipeline latency is 66 clock cycles.