{"title":"基于Verilog HDL的2D-DCT安全图像压缩FPGA实现","authors":"B. Jeevan, C. N. Bhatt, C. V. Krishna, K. Sivani","doi":"10.1109/ICDCSYST.2014.6926210","DOIUrl":null,"url":null,"abstract":"The Secure Image Compression consists of JPEG encoder in which 2D-DCT (2Dimensional - Discrete Cosine Transform) is used to provide security while compressing the image. In this paper Verilog design and hardware implementation of pipelined 2-D DCT are described. The architecture uses 4327 slices, 7621 LUTs, 25 I/Os of FPGA Spartan3E-XC3S500E and works at an operating frequency of 89.469MHz. The delay of processing each 8*8 block in an image is evaluated to be 9.167ns and pipeline latency is 66 clock cycles.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"FPGA implementation of secure image compression with 2D-DCT using Verilog HDL\",\"authors\":\"B. Jeevan, C. N. Bhatt, C. V. Krishna, K. Sivani\",\"doi\":\"10.1109/ICDCSYST.2014.6926210\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Secure Image Compression consists of JPEG encoder in which 2D-DCT (2Dimensional - Discrete Cosine Transform) is used to provide security while compressing the image. In this paper Verilog design and hardware implementation of pipelined 2-D DCT are described. The architecture uses 4327 slices, 7621 LUTs, 25 I/Os of FPGA Spartan3E-XC3S500E and works at an operating frequency of 89.469MHz. The delay of processing each 8*8 block in an image is evaluated to be 9.167ns and pipeline latency is 66 clock cycles.\",\"PeriodicalId\":252016,\"journal\":{\"name\":\"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-03-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICDCSYST.2014.6926210\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICDCSYST.2014.6926210","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA implementation of secure image compression with 2D-DCT using Verilog HDL
The Secure Image Compression consists of JPEG encoder in which 2D-DCT (2Dimensional - Discrete Cosine Transform) is used to provide security while compressing the image. In this paper Verilog design and hardware implementation of pipelined 2-D DCT are described. The architecture uses 4327 slices, 7621 LUTs, 25 I/Os of FPGA Spartan3E-XC3S500E and works at an operating frequency of 89.469MHz. The delay of processing each 8*8 block in an image is evaluated to be 9.167ns and pipeline latency is 66 clock cycles.
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