2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)最新文献_第7页

Modelling and investigation of III-V compound semiconductor based HEMT's for high performance applications 基于III-V型化合物半导体的高性能HEMT的建模和研究

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926123

T. Subash, T. Gnanasekaran, D. Nirmal, A. Johnson

引用次数: 0

Comparison of LSB based and HS based reversible data hiding techniques 基于LSB和HS的可逆数据隐藏技术的比较

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926152

Shri Lakshmi Pravalika, C. S. Joice, A. Raj

引用次数: 4

Empirical model of flicker due to vertical wind shear instigated by civilization in a seashore wind turbine using wind tunnel 海岸带风力机文明垂直风切变闪变的风洞经验模型

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926199

Dr. Prof. Datta S Chavan Ph.D., Aditi Rana, Mahal Raj Singh, P. Karandikar, S. D. Bhide

引用次数: 28

Electrical transport in graphene nanoribbon interconnect 石墨烯纳米带互连中的电输运

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926148

S. Bhattacharya, Subhajit Das, Debaprasad Das, H. Rahaman

引用次数: 1

Modified whirlpool hash based bloom filter for networking and security applications 修改了基于网络和安全应用的漩涡哈希的布隆过滤器

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926138

K. Saravanan, A. Senthilkumar, Preethi Chacko

{"title":"Modified whirlpool hash based bloom filter for networking and security applications","authors":"K. Saravanan, A. Senthilkumar, Preethi Chacko","doi":"10.1109/ICDCSYST.2014.6926138","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926138","url":null,"abstract":"Bloom is an efficient data structure technique. Initially it was used in intelligent dictionaries and spell check applications. Its ability for dynamic membership querying and information compaction attracted huge research. Various optimization models of bloom filter for diverse applications were suggested and hence many bloom filter variants emerged. Network security has become an important factor in the recent years. In this paper, we propose a new variant of bloom filter in which a standard cryptographic hash function whirlpool is modified into a non cryptographic form and deployed in the bloom filter to improve the network security. We also suggest a suitable mapping scheme. A cryptographic hash function is one which converts an input data of arbitrary length into a fixed-length output. Bloom Filters are hash based structures which have a certain degree of accuracy for considerable savings in memory and are used to support membership queries. Bloom Filters allow probability of False Positive Ratios and the aim of this paper is to reduce FPR by modifying the structure of bloom filter and enabling it to operate in the increasing network speed. The design has been implemented and tested using a Xilinx 65 nm field programmable gate array as the target technology and the results are compared with replacing the housing unit with widely used universal H3 hash function and also relatively compared with the other possible hash functions and bloom filters in literature. The performance matrices of the proposed design are false positive ratio and speed. The design is hardware based and suitable for networking and security querying applications.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131279407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Reconfigurable edge detection processor using Xilinx Platform Studio 使用Xilinx Platform Studio的可重构边缘检测处理器

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926135

B. Muralikrishna, G. L. Madhumati, Habibulla Khan, K. Deepika

引用次数: 0

Exposure fusion for concealed weapon detection 用于隐蔽武器探测的暴露融合

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926141

Ekta M. Upadhyay, N. Rana

引用次数: 16

Intelligent controller based three phase shunt active filter for THD reduction in non-linear load and capacitor voltage stability 基于智能控制器的三相并联有源滤波器在非线性负载和电容电压稳定中降低THD

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926144

K. A. Rani Fathima, T. A. Raghavendiren

{"title":"Intelligent controller based three phase shunt active filter for THD reduction in non-linear load and capacitor voltage stability","authors":"K. A. Rani Fathima, T. A. Raghavendiren","doi":"10.1109/ICDCSYST.2014.6926144","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926144","url":null,"abstract":"This study presents on a shunt active filter (SAF) for the power quality enhancement and voltage stability in the power systems. The main aim is to investigate the various control methodologies for the compensation of current harmonics, voltage stability and the reactive power owing to the non-linear loads at various operating conditions. In addition, in this paper one of the intelligent controller like fuzzy logic controller (FLC) and proportional integral controller (PIC) is applied for the stabilizing the DC bus capacitor voltage during the transient as well steady state conditions. The reference currents are extorted from the unit sine vector multiplied with the approximated peak reference current. The voltage source inverter P W M gating switching signals are generated through the hysteresis current controller (HCC). The performance of SAF is validated through MATLAB/Simulink simulation at different conditions using designed controllers. The theoretical analysis, design and simulation results are demonstrate that the designed FLC is produced stabilized DC bus capacitor voltage under the transient region., and also the suppresses the current harmonics in the supply side.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131030039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An analytical approach for quadrant based leach: An energy efficient routing protocol for WSNs 基于象限的浸出分析方法:无线传感器网络的节能路由协议

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926117

J. Gnanambigai, N. Rengarajan, R. Prarthana

{"title":"An analytical approach for quadrant based leach: An energy efficient routing protocol for WSNs","authors":"J. Gnanambigai, N. Rengarajan, R. Prarthana","doi":"10.1109/ICDCSYST.2014.6926117","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926117","url":null,"abstract":"Wireless Sensor Network (WSN) is an emerging network technology that provides reputable monitoring of the various environmental circumstances. One among the paramount constrains in the WSN is it's scrimp energy resource. Many experimental works in WSNs are focussed towards achieving energy efficacy. Though there are various assortments in WSN that would appealingly achieve energy efficient operation the section of routing schemes proves to be a demanding field of research. There are several denominations of routing protocols available and the class of hybrid routing protocols are the ones that are the combos of two different genres of routing protocol. Though Low Energy Adaptive Clustering Hierarchy (LEACH) proves to be an outwitting routing scheme there are inherent limitations due to the power hungry overhead processing and the more number of participating nodes. This paper focuses towards the development of a new genre of hybrid routing protocol that collides the LEACH (Hierarchical routing protocol class of WSN) and the Quadrant based Directional Routing (Q-DIR) (Ad-hoc Routing scheme). This new scheme outdoes the shortcomings of the LEACH and assures energy efficient operation with extends the network lifetime. In addition to this the paper also works on the energy parameters concordant to the protocol operation.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"19 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129868525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Design of high speed DDR SDRAM controller with less logic utilization 逻辑利用率低的高速DDR SDRAM控制器设计

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926129

Pooran Singh, B. Reniwal, V. Vijayvargiya, S. Vishvakarma

{"title":"Design of high speed DDR SDRAM controller with less logic utilization","authors":"Pooran Singh, B. Reniwal, V. Vijayvargiya, S. Vishvakarma","doi":"10.1109/ICDCSYST.2014.6926129","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926129","url":null,"abstract":"This paper focuses on controlling synchronous dynamic random access memory (SDRAM) higher data transfer rates when multiple locations in internal memory array are accessed successively. The controller is designed to interface DDR memory modules and memory ICs with low cost FPGAs and high clock frequency of 674.491 MHz at 28nm technology on Kintex 7 FPGA device with less logic utilization. The DDR controller makes many low level tasks invisible to the user like refresh, initialization and timings. It provides another layer of abstraction by optimizing memory access for maximum throughput or minimum latency. DDR controller provides the access of memory banks in parallel form, so it is required to being fast with less logic utilization. This paper optimizes the DDR SDRAM controller design by structural RTL level HDL Coding and modelling of SDRAM Initializing finite state machine (FSM). The results show 0.33% of slice utilization and 0.14% of LUT utilization is recorded at Xilinx Virtex 7 low voltage FPGA device. Due to RTL level optimization the route delay is just about 30% to 38 % as compare to that of logic delay. We also observe that the Kintex 7 Xilinx FPGA device has low offset input and output delay of the clock clk100 and clk200 of data path in this logic as compare to other FPGA devices. So hereby we proposed a DDR SDRAM controller which can work at high speed with less logic utilization and minimum logic, route and offset delay.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128686206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4