{"title":"Modelling and investigation of III-V compound semiconductor based HEMT's for high performance applications","authors":"T. Subash, T. Gnanasekaran, D. Nirmal, A. Johnson","doi":"10.1109/ICDCSYST.2014.6926123","DOIUrl":null,"url":null,"abstract":"This paper investigates indium antimonide based quantum well field effect transistors with 40 nm physical gate length. Self consistent T-CAD simulations are used to study the high-speed potential of InSb field-effect transistors and its suitable for high speed, very low power logic applications. At the room temperature electron mobility in excess of 30,000 cm2/V-1s-1 in material with sheet carrier density typical of that employed in analogue transistors. 40nm gate length is used to obtain maximum drain current of 6.4e-4A/μm and the threshold voltage of the device is found to be -0.5V. The maximum drain current is found to be 6.4e-4 for the doping concentration of 1e+19. The OFF current of the device is found to be 2.642e-07A/μm when the gate voltage increases beyond 0.2V.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICDCSYST.2014.6926123","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper investigates indium antimonide based quantum well field effect transistors with 40 nm physical gate length. Self consistent T-CAD simulations are used to study the high-speed potential of InSb field-effect transistors and its suitable for high speed, very low power logic applications. At the room temperature electron mobility in excess of 30,000 cm2/V-1s-1 in material with sheet carrier density typical of that employed in analogue transistors. 40nm gate length is used to obtain maximum drain current of 6.4e-4A/μm and the threshold voltage of the device is found to be -0.5V. The maximum drain current is found to be 6.4e-4 for the doping concentration of 1e+19. The OFF current of the device is found to be 2.642e-07A/μm when the gate voltage increases beyond 0.2V.