2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)最新文献_第6页

Recognizing facial images using Gabor Wavelets, DCT-Neural Network, Hybrid Spatial Feature Interdependence Matrix 基于Gabor小波、dct -神经网络、混合空间特征相互依赖矩阵的人脸图像识别

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926130

S. Fernandes, G. J. Bala

引用次数: 12

QCA system design using blocks with vertically stacked active elements QCA系统设计采用块与垂直堆叠的有源元素

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926132

N. Kumari, K. Gurumurthy

{"title":"QCA system design using blocks with vertically stacked active elements","authors":"N. Kumari, K. Gurumurthy","doi":"10.1109/ICDCSYST.2014.6926132","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926132","url":null,"abstract":"Quantum Dot Cellular Automata is one among the various technologies proposed by the International Technology Roadmap for Semiconductors (ITRS) as a viable alternative to CMOS. Circuits designed in QCA are potentially better with respect to speed, power and area when compared to their counter parts in CMOS. But as the circuit complexity increases, there is a linear growth in the horizontal area leading to lengthier interconnects with increased delay. To circumvent this problem we propose a new design paradigm using vertically stacked QCA cells. As the active elements are placed right one above the other in this new approach, the number of cells used for the interconnection will be drastically reduced. Thus would result in very compact designs. This technique provides greater flexibility in routing due to the availability of both vertical and horizontal planes. Each majority gate which forms the basic element of a QCA circuit/Block is implemented in a different layer; hence it explores a new concept of reusability in QCA along with the reduction of time for determination of errors. In this paper we establish this idea with the design of adders, subtractors, ripple adders, ripple adder cum subtractors using vertically stacked QCA circuits. These circuits are implemented using the least number of cells and minimum clocking zones. Results obtained by simulation show a maximum reduction in the number of cells used for the overall design by 77% and the cells used for the interconnection by 90% in comparison to their primitive counterparts respectively.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117191868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effective binary to BCD converter using QuantumDot Cellular Automata 使用量子点元胞自动机的有效二进制到BCD转换器

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926118

A. Sasikala, S. Maragatharaj, S. Jayadevi

引用次数: 4

Switching performance analyses of gate material and gate dielectric engineered TFET architectures and impact of interface oxide charges 栅极材料和栅极电介质工程TFET结构的开关性能分析及界面氧化物电荷的影响

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926182

Upasana, R. Narang, M. Saxena, Mridula Gupta

{"title":"Switching performance analyses of gate material and gate dielectric engineered TFET architectures and impact of interface oxide charges","authors":"Upasana, R. Narang, M. Saxena, Mridula Gupta","doi":"10.1109/ICDCSYST.2014.6926182","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926182","url":null,"abstract":"In this work performance investigation of three different Double Gate n-type TFET architectures i.e. Dual material Gate (DMG) TFET, Hetero-Dielectric (H-D) TFET and Dual Material Hetero-Dielectric (DMG H-D) TFET has been performed for Digital Circuit Applications. Moreover, a comparative study among these three aforementioned device architectures has been made in terms of performance metrics such as Total gate Capacitance (Cgg), Miller capacitance (Cgd), fall propagation delay (tpHL) and peak overshoot voltage (Vp). In this regard, exhaustive simulations have been done through Atlas Device Simulator. Furthermore, the impact of metal gate (M1) work function and length L1 variation over device switching characteristics has also been observed. Impact of Interface oxide charges (positive and negative) on the transient behavior, threshold voltage, Ion, Ioff, Ion/Ioff has also been studied for all three device architectures. It has been investigated that DMG H-D TFET which is the proposed architecture outperforms other devices i.e. DMG TFET and H-D TFET in terms of comparatively lower value of tpHL, Vp and miller capacitance Cgd.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117239878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Reduction of reflectance at c-silicon solar cell using nanotexturization 利用纳米化技术降低c-硅太阳能电池的反射率

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926171

S. Maity, A. Kundu, Sonali Das, P. Chakraborty

引用次数: 1

Simple nonautonomous Wien-bridge oscillator based chaotic circuit 基于简单非自治温桥振荡器的混沌电路

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926121

R. Rizwana, I. R. Mohamed, K. Srinivasan, M. Inbavalli

引用次数: 4

Ultra-low power circuit design using double-gate FinFETs 采用双栅极finfet的超低功耗电路设计

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926194

G. Devi Tejashwini, I. B. K. Raju, G. Chary

引用次数: 4

Optical properties of samarium doped ZnO thin films 钐掺杂ZnO薄膜的光学性质

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926170

T. Rao, S. G. Raj, M. C. Santhosh Kumar

引用次数: 4

Coiflets, artificial neural networks and predictive coding based hybrid image compression methodology 基于coiflet、人工神经网络和预测编码的混合图像压缩方法

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926208

S. Sridhar, P. R. Kumar, K. Ramanaiah, D. Nataraj

{"title":"Coiflets, artificial neural networks and predictive coding based hybrid image compression methodology","authors":"S. Sridhar, P. R. Kumar, K. Ramanaiah, D. Nataraj","doi":"10.1109/ICDCSYST.2014.6926208","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2014.6926208","url":null,"abstract":"Hybrid image compression system is discussed and analyzed for better objective fidelity metrics combining the advantages of Coiflet filter functions of wavelets, Predictive Coding (Differential Pulse Code Modulation-DPCM) and neural networks in addition to quantization and Huffman encoding techniques to eliminate the interpixel, psychovisual redundancy and coding redundancy. Artificial neural networks are self adaptive i.e. they can adjust themselves to data without any specification of the functional model they are fault tolerant by architecture. Wavelets (by choice) on the other hand are computationally simple and provide good compression ratios for high resolution images especially while DPCM removes redundancy in the information. Initially selected wavelet of choice (Coiflet5 in this case) is applied on the input image for two level decomposition generating seven bands of low frequency and high frequency coefficients. The low frequency band 1 coefficients are compressed with DPCM technique while the remaining bands of coefficients are compressed with artificial neural networks. Metrics obtained: Peak Signal to Noise Ratio (PSNR) Mean Square Error (MSE) and Compression Ratio (CR) are tabulated for comparative analysis.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123853224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Low hardware overhead implementation of 3-weight pattern generation technique for VLSI testing VLSI测试中三权重模式生成技术的低硬件开销实现

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI: 10.1109/ICDCSYST.2014.6926180

D. Gracia Nirmala Rani, M. G. Mangala Meenakshi, S. Marina

引用次数: 2