Low hardware overhead implementation of 3-weight pattern generation technique for VLSI testing

Abstract

Pseudorandom Built-In Self-Test (BIST) generators have been most frequently used to test the integrated circuits and systems. This scheme requires more test patterns and consumes more testing time hence weighted pseudorandom BIST schemes have been proposed. These methodologies are used to drive down the number of test vectors. Most of the current VLSI chips have accumulators; hence they can be utilized efficiently to reduce the hardware of BIST pattern generation. Therefore in this paper a low hardware overhead implementation of 3-weight pattern generation technique is proposed to achieve high fault coverage and reduced testing time. The proposed scheme generates set of patterns for ISCAS c17 benchmark circuits with weights 0, 0.5, and 1.