采用双栅极finfet的超低功耗电路设计

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS) Pub Date : 2014-03-06 DOI:10.1109/ICDCSYST.2014.6926194

G. Devi Tejashwini, I. B. K. Raju, G. Chary

{"title":"采用双栅极finfet的超低功耗电路设计","authors":"G. Devi Tejashwini, I. B. K. Raju, G. Chary","doi":"10.1109/ICDCSYST.2014.6926194","DOIUrl":null,"url":null,"abstract":"In this paper, the design and performance of basic Digital (AND, OR, NAND, NOR, XOR, XNOR, NOT, Half-Adder) and Analog (Current Mirror, Cascode Current Mirror, Comparator) circuits using 20nm FinFET technology has presented. 20nm FinFET technology has been used for improvement in performance and for optimizing power mainly in Analog circuits. In this work, for different widths of NMOS and PMOS and low voltages, better results of power performance is observed in both digital and analog circuits using FinFET technology.","PeriodicalId":252016,"journal":{"name":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Ultra-low power circuit design using double-gate FinFETs\",\"authors\":\"G. Devi Tejashwini, I. B. K. Raju, G. Chary\",\"doi\":\"10.1109/ICDCSYST.2014.6926194\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the design and performance of basic Digital (AND, OR, NAND, NOR, XOR, XNOR, NOT, Half-Adder) and Analog (Current Mirror, Cascode Current Mirror, Comparator) circuits using 20nm FinFET technology has presented. 20nm FinFET technology has been used for improvement in performance and for optimizing power mainly in Analog circuits. In this work, for different widths of NMOS and PMOS and low voltages, better results of power performance is observed in both digital and analog circuits using FinFET technology.\",\"PeriodicalId\":252016,\"journal\":{\"name\":\"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-03-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICDCSYST.2014.6926194\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICDCSYST.2014.6926194","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

本文介绍了采用20nm FinFET技术的基本数字电路(and、OR、NAND、NOR、XOR、XNOR、NOT、半加法器)和模拟电路(电流镜、cascade电流镜、比较器)的设计和性能。20nm FinFET技术主要用于模拟电路的性能改进和功率优化。在这项工作中，对于不同宽度的NMOS和PMOS以及低电压，使用FinFET技术在数字和模拟电路中都观察到更好的功率性能结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Ultra-low power circuit design using double-gate FinFETs

In this paper, the design and performance of basic Digital (AND, OR, NAND, NOR, XOR, XNOR, NOT, Half-Adder) and Analog (Current Mirror, Cascode Current Mirror, Comparator) circuits using 20nm FinFET technology has presented. 20nm FinFET technology has been used for improvement in performance and for optimizing power mainly in Analog circuits. In this work, for different widths of NMOS and PMOS and low voltages, better results of power performance is observed in both digital and analog circuits using FinFET technology.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)

自引率

0.00%

发文量