{"title":"Hydrolytically stable aluminum nitride as a filler material for polymer based electronic packaging","authors":"K. E. Howard, A. Knudsen","doi":"10.1109/ISAPM.1997.581266","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581266","url":null,"abstract":"A new filler material, SCAN, silica-coated aluminum nitride, has been developed by The Dow Chemical Company for microelectronic plastic packaging. SCAN is a hydrolytically stable aluminum nitride material with appropriate particle size distribution and thermal conductivity to be used as a filler material for molding compounds or glob-tops where power dissipation is required. The patented silica coating process imparts hydrolytic stability to the powder and modifies the surface chemistry to make it more compatible with resin formulations that have traditionally used fused silica.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126996198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Materials in next generation of packaging","authors":"R. Tummala, C. Wong","doi":"10.1109/ISAPM.1997.581241","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581241","url":null,"abstract":"The Packaging Research Center (PRC) was established to explore, develop, and prototype the next generation of electronic packaging technologies and to produce a new breed of globally competitive engineers thereby providing both the technological and human resources necessary to enable 10/spl times/ improvements in size, cost, performance, and reliability of next generation electronic products. The research vision parallels what integrated circuits did for transistors - ever increasing integration while maintaining constant manufacturing costs. The strategy is a systems-level approach with a balanced combination of fundamental, applied, cross-disciplinary, and prototype research to overcome the technological barriers. The cross-disciplinary research efforts are integrated into four focused research areas: (1) Systems Integration, Design, and Test; (2) Low-cost, Integrated Substrate; (3) Optoelectronics and Wireless Electronics; and (4) Assembly, Reliability, and Thermal Management. Materials form the \"heart and soul\" of next generation of packaging and include enhanced materials for printed wiring board, interlayer dielectrics, integrated capacitors, resistors and inductors, flipchip solder joints and alternatives, underfills and encapsulants and heat-transfer materials.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116512359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel thick film materials technology offering high performance packaging solutions","authors":"P. Barnwell","doi":"10.1109/ISAPM.1997.581285","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581285","url":null,"abstract":"Thick film technology has been widely used in the past for modern performance packaging solutions, but has been unable to complete with thin film technology for high performance requirements. The problems of poor geometrical resolution, together with high dielectric constant and loss have all contributed to the very limited adoption of thick film for advanced packaging. This paper describes an advanced ceramic based technology using thick film conductors and dielectric. Excellent geometrical properties result from a combination of novel materials and processing, giving line widths better than 25 micron and via geometries better than 50 micron. A novel dielectric material provides a dielectric constant of less than 4, with a loss factor better than 1.10/sup -4/. This technology allows the fabrication of high density circuits and packages, offering many packaging solutions, including MCM, microwave, sensors and displays, all on one substrate. The paper discusses the technology, its processing and performance. It concludes by presenting examples of typical applications.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132796820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Characterizing the failure envelope of a conductive adhesive","authors":"D. Olliff, M. Gaynes, R. Kodnani, A. Zubelewicz","doi":"10.1109/ISAPM.1997.581274","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581274","url":null,"abstract":"The importance of flip chip technology is beginning to grow as the use of such technology is seen to be more and more advantageous. The search for alternatives to lead-based solder has also led to the study of conductive adhesives as a possible replacement for solder interconnect technology. Under a grant from DARPA, the IBM and Universal Instruments Corporations have sought to create a flip chip package using conductive adhesive interconnects. This paper presents the preliminary results of mechanical testing designed to determine the static failure envelope of the adhesive. A difference in fracture mode was observed between the tensile and compressive samples indicating that a change in failure mechanism occurred. Further work is being conducted in order to isolate the specific failure mechanisms involved.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115521575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A screen printable silicone-imide paste for high performance coatings and adhesives","authors":"Jin-O Choi, R. Kirsten, S. Rojstaczer, D. Riordan","doi":"10.1109/ISAPM.1997.581255","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581255","url":null,"abstract":"Summary form only given. A novel screen printable paste has been developed for use as a patterned protective coating or adhesive. This high purity, high solid content paste is based on a high temperature, thermoplastic silicone-imide resin that provides good thermal stability, low water absorption and hot-melt adhesion. By using either a stencil or a screen, a good resolution pattern can be obtained for a 60 /spl mu/m thick baked layer. The fully cured coatings show low moisture absorption and excellent mechanical properties. The glass transition temperature is 165/spl deg/C. The fully cured coatings can be bonded to alloy 42 metal substrate by laminating at 250/spl deg/C. The paste can be used in non-conductive die-attach applications as well as an overcoat protective layer over rigid or flexible circuits.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125868977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mechanical properties of Sn-In and Pb-In solders at low temperature","authors":"W. Jones, Y.Q. Liu, M. Shah","doi":"10.1109/ISAPM.1997.581258","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581258","url":null,"abstract":"The growing number of applications using high temperature superconductors (HTS) has created new requirement for increasing the range of temperatures in which electronic assemblies can operate. Typically, eutectic lead-tin solders lose ductility below -150/spl deg/C. In this paper, new solder formulations were evaluated for cryogenic applications. The mechanical properties of PbIn and Sn-In solders were determined over the temperature range -200/spl deg/C to 100/spl deg/C using the uniaxial tensile test, with the following results. The strength of two types of solder increases almost linearly with decreasing temperature. However, it was evident that the Sn-In alloying solders possess higher strength than the Pb-In (50 Pb/50 In) solder at low temperatures. For both types of solder, the total elongation decreases with decreasing temperature, and all of the solders displayed superplasticity at temperatures greater than 50/spl deg/C. There was also doubling of the uniform elongation below -50/spl deg/C for all of the tested solders. The deformation and fracture processes of the solders were investigated, and their fracture mechanism is proposed.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122453492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Advanced encapsulation processing for low cost electronics assembly-a cost analysis","authors":"N. W. Pascarella, D. Baldwin","doi":"10.1109/ISAPM.1997.581253","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581253","url":null,"abstract":"Major cost driving factors for current advanced electronics assembly processes are polymer encapsulation and polymer dispensing processing. This is particularly true for flip chip on board interconnection technology. As an integral part of the Low Cost Next Generation Flip Chip Processing Program of Georgia Tech's Packaging Research Center, a preliminary industry benchmark study has been conducted to determine high cost process characteristics of state-of-the-art flip chip assembly technology. The benchmarking analysis has identified certain steps of the assembly process as high cost including bumping, underfill dispensing and curing of underfill material. Based on these cost factors, a new flip chip assembly process concept has been developed to reduce process steps, process time, and cost. A cost model has been created to analyze the new assembly process and compare it with current benchmark processes. Leveraging the cost analysis, further cost reducing refinements to the process have been identified achieving a low cost solution. The work presented will focus on flip chip assembly cost analysis and process design.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131022209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integration of polymer/ceramic thin film capacitor on PWB","authors":"S. Bhattacharya, R. Tummala, P. Chahal, G. White","doi":"10.1109/ISAPM.1997.581259","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581259","url":null,"abstract":"Electrical properties of various polymer-ceramic composites have been studied for use in integrated capacitors on PWB substrates. The dielectric constant of the composite is strongly dependent on the individual properties of polymer and ceramic materials. Epoxy is the material of choice for its compatibility with PWBs. Further, epoxy materials are not attacked by high PH environment during electroless plating of the capacitor electrodes. Photodefinable and nonphotodefinable materials have been evaluated for capacitor integration on PWBs using thin-film processes and screen printing. Lead magnesium niobate is selected as the filler material for its high dielectric constant value and its compatibility with most polymers.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122941492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electrical performance in time domain of subminiature interconnections on new thin films","authors":"R. Salik, P. Ferrari, A. Chosson, G. Angnieux","doi":"10.1109/ISAPM.1997.581279","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581279","url":null,"abstract":"This paper is focused on transmission lines with dimensions comparable to future VLSI interconnections (except for the transmission line width which is equal to 5 /spl mu/m, whereas the width of future interconnections will probably be less than 1 /spl mu/m). The goal is to show on which characteristic the effort must be made. To achieve this, the propagation of fast signals along the transmission lines is studied in the time domain. The effect of the insulator on electrical delay and distortion are pointed out. A Fourier transform is used to give the propagation constant /spl gamma/(/spl omega/)=/spl alpha/(/spl omega/)+j/spl beta/(/spl omega/) of the transmission lines in the frequency domain. Results are compared to those obtained by a full wave frequency domain modeling method (TRM).","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114388130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Primerless RTV silicones for electronic protection","authors":"B. Van Wert, J. Fiori","doi":"10.1109/ISAPM.1997.581254","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581254","url":null,"abstract":"This paper describes a new silicone potting compound, which has been formulated to deliver fast, room-temperature vulcanizing (RTV) cure and excellent adhesion to most common metals and plastics in electronics applications. Dow Corning/sup (R/) 3-4207 Gel has been tested with good results on aluminum, alumina, and copper, as well as PET, FR4 board, and PPS. The material has demonstrated excellent performance on the high-temperature epoxy glass laminates used in circuit board manufacturing. With difficult substrates, a 15-30 minute cure cycle at 60-80 /spl deg/C has been shown to produce excellent interfacial adhesion.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"96 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116609003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}