Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces最新文献

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Trends in lead frame technology for plastic packaging 塑料包装引线框架技术的发展趋势
D. Mahulikar
{"title":"Trends in lead frame technology for plastic packaging","authors":"D. Mahulikar","doi":"10.1109/ISAPM.1997.581265","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581265","url":null,"abstract":"Lead frames make up the largest portion of the materials costs in plastic packages; especially Quad Flat Packages (QFP's). For stamping lead frames the costs can be up to 60% of total while for etched lead frames it can run up to 75% of total. Additionally, from performance perspectives lead-frames are a critical component of the packaging system. Lead frames must be strong to withstand handling, yet compliant to tolerate bending. They must have high thermal conductivity to dissipate heat generated by the IC device and good electrical properties so as not to deteriorate the IC device performance. In addition, lead frames are a critical part of the reliability of the overall packaging system. Lead frame properties can affect solder joint fatigue, delamination in moisture tests, and wire bonding integrity. The SIA and SEMATECH packaging road maps represent significant new challenges for lead frames. In upcoming years not only lead frame materials will have to be stretched to their limits, but it will have to be done much more cost effectively. The TRP Low-Cost Packaging Consortium looked at two critical areas: very high strength reasonable conductivity alloy development and adhesion improvements for delamination resistance. This paper discusses lead frame technology trends to the year 2000 and TRP development work to date.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132793354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new design-for-reliability approach to thermal fatigue life prediction of leadless solder joints 无铅焊点热疲劳寿命预测的可靠性设计新方法
Y. Pao, E. Jih, R. Liu, V. Siddapureddy, X. Song, R. McMillan, J.M. Hu
{"title":"A new design-for-reliability approach to thermal fatigue life prediction of leadless solder joints","authors":"Y. Pao, E. Jih, R. Liu, V. Siddapureddy, X. Song, R. McMillan, J.M. Hu","doi":"10.1109/ISAPM.1997.581276","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581276","url":null,"abstract":"Summary form only given. While a tremendous amount of work has been done in leadless solder joint reliability, the detailed thermal fatigue failure mechanisms and their relations with key parameters, e.g., solder fillet, inner end geometry, and microstructure, have, however, not yet been fully understood. Also life prediction methodologies that account for the physics of failure still remain to be developed. In this paper the failure mechanisms of 2512 LCR solder joints are discussed based on thermal fatigue test results, and reliability models for fatigue crack initiation and propagation and the effect of solder height are elaborated.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"137 2-3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131520806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Practical applications of photo-defined micro-via technology (PhotoLink/sup TM/) 照片定义微孔技术的实际应用(PhotoLink/sup TM/)
B. McDermott, Sid Tryzbiak
{"title":"Practical applications of photo-defined micro-via technology (PhotoLink/sup TM/)","authors":"B. McDermott, Sid Tryzbiak","doi":"10.1109/ISAPM.1997.581246","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581246","url":null,"abstract":"Current high density SMT designs and many of the future designs, as we move towards Chip-Scale Packaging (CSP), will require increased price/performance of the PCB. Conventional mechanical drilling and blind/buried via technologies are reaching their design limitations. Photoimageable dielectrics may be the most cost effective and the least time to market of the higher density technologies. This is a fundamental change in the way we make PCB's. It will provide the process capability in terms of via size to meet the longer term interconnect density requirements. This technology is available today to enable the implementation of higher density SMT and CSP designs. It provides significant advantages in terms of physical design rules and also electrical design.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134515090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Colamination technology for electronic packaging applications 用于电子封装的叠合技术
S. Leach, C.N. Ernsberger
{"title":"Colamination technology for electronic packaging applications","authors":"S. Leach, C.N. Ernsberger","doi":"10.1109/ISAPM.1997.581250","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581250","url":null,"abstract":"\"Colamination\" is a packaging technology that, in many ways, is a cost effective organic version of Cofire ceramic. The Colamination process and material sets have been in development at CTS for several years. An extensive reliability database has been developed for Colaminated substrates through fabrication of various test vehicles and prototypes. Recent work by CTS involves qualification of Colaminated substrates in several customer applications. This abstract briefly describes Colamination technology and some prototype work CTS has been involved with. We also describe some recent technical developments in Colamination technology.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131151947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Laser machining of ceramics and silicon for MCM-D applications 用于MCM-D应用的陶瓷和硅激光加工
V. Glaw, R. Hahn, A. Paredes, U. Hein, O. Ehrmann, H. Reichl
{"title":"Laser machining of ceramics and silicon for MCM-D applications","authors":"V. Glaw, R. Hahn, A. Paredes, U. Hein, O. Ehrmann, H. Reichl","doi":"10.1109/ISAPM.1997.581287","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581287","url":null,"abstract":"The ceramics were machined with a computer controlled Nd:YAG slab-laser. The laser parameters as well as the process parameters were optimized to obtain kerfs with good quality and cuts without cracks. Two applications were investigated: ceramics and silicon as substrates for embedded MCM-Ds (Multi Chip Modules, Deposited) and water-cooled heat sinks for single chips, multichip modules or laser diodes. For the embedded MCMs, windows were machined into the substrate. Bare dice and standard passive components (like capacitors or resistors) were inserted into these windows and fixed in their position with an epoxy. AlN, Al/sub 2/O/sub 3/ and Si were tested as substrate materials. The critical parameter was the mechanical stability of the substrate because of the thermal stress introduced by the following thin film process. For the second application, several heat sinks were produced in AlN. Different methods to clean the cooling channels were investigated. Maximum heat dissipation of water-cooled test-devices was determined for various channel geometries.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"368 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133635204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Molecular insights on interfacial properties and moisture uptake of plastic packaging materials 塑料包装材料界面特性和吸湿性的分子研究
M. Schen, Wen-Li Wu, W. Wallace, N. Beck-Tan, D. Vanderhart, G. T. Davis
{"title":"Molecular insights on interfacial properties and moisture uptake of plastic packaging materials","authors":"M. Schen, Wen-Li Wu, W. Wallace, N. Beck-Tan, D. Vanderhart, G. T. Davis","doi":"10.1109/ISAPM.1997.581263","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581263","url":null,"abstract":"Product trends such as chip scale packaging and high density electronic interconnects are driving technologies towards increased complexity and reduced feature sizes. Two particularly important technical challenges involving plastic packages are to enhance the robustness of multi-component material interfaces and to improve the resistance of plastic assemblies to the effects of moisture. This presentation will review recent insights gained at NIST within its electronic packaging, interconnection and assembly program. First, a discussion of the properties and moisture susceptibility of buried polymer interfaces is presented. Using neutron and X-ray reflectivity techniques, NIST can directly measure the CTE and hygroscopic expansion of extremely thin polymer films. Neutron techniques can also yield information about the concentration profile of deuterated water near an interface. Second, results from moisture uptake and egress studies within a molding compound are also presented. Using solid state NMR, NIST can detect different forms of absorbed water and observe how this water responds to changes in the external environment.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114303031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Advanced encapsulant systems for flip chip 用于倒装芯片的先进封装系统
D. Gamota, C. Melton
{"title":"Advanced encapsulant systems for flip chip","authors":"D. Gamota, C. Melton","doi":"10.1109/ISAPM.1997.581252","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581252","url":null,"abstract":"Flip chip on board (FCOB) technology is a novel electronic assembly structure whereby a bare integrated circuit (IC) die is interconnected directly to an organic printed circuit board (PCB). Mechanical coupling of the die and PCB by an epoxy encapsulant enhances the performance of the FCOB assembly during reliability testing. Advanced encapsulant materials for FCOB must address the issues observed during assembly of consumer electronic products on a high volume manufacturing line. The development of these materials is critical to continue the integration of FCOB assemblies as an alternative packaging system in electronic products. Materials characterization studies were performed to determine the glass transition temperatures (Tg), tensile elastic and loss moduli (E' and E\"), flow profiles, coefficients of thermal expansion (CTE), and apparent strengths of adhesion for several advanced encapsulants. In addition, reliability tests were conducted to observe the relationship between encapsulant materials properties and reliability responses.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114687295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Low cost solder flip chip 低成本焊料倒装芯片
G. Rinne, P. Magill
{"title":"Low cost solder flip chip","authors":"G. Rinne, P. Magill","doi":"10.1109/ISAPM.1997.581270","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581270","url":null,"abstract":"Since the advent of flip chip packaging technology in the solid logic technology (SLT) of IBM in the early 1960s, a great deal of thought and energy has been invested toward making flip chip cost competitive with wirebonding. While this goal has been occasionally met in the intervening years, the relentless progress of wirebond technology has repeatedly regained the advantage.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125216475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A comprehensive study on 40-mil PBGA 40mil PBGA的综合研究
R. T. Chen, Yukon Chou, T. Ho, P. Chiang, C. Chao, Wun-Yan Chen
{"title":"A comprehensive study on 40-mil PBGA","authors":"R. T. Chen, Yukon Chou, T. Ho, P. Chiang, C. Chao, Wun-Yan Chen","doi":"10.1109/ISAPM.1997.581257","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581257","url":null,"abstract":"The 40-mil PBGA is an effective application for higher I/O density. In regular consideration, the pad size and the solder sphere should be smaller due to decreasing the bump pitch from 50 or 60 mils to 40-mil PBGA. Until now, we could not find any standard product or paper which refers to pad size and solder sphere diameter. So we setup this experiment to find out the results and hope it will be useful to build-up the optimal bumping process of 40-mil PBGA. In this study, we considered many different factors such as substrate pad size and solder sphere diameter. In order to find out the best combination of all these factors to achieve the highest manufacturing yield, we applied the thermocouple technology to measure the thermal distribution of the entire substrate in reflow furnace. After bumping the solder ball onto the substrate, we use ball shear test to analyze the force difference between the balls caused by different temperature profile. The shear height and shear speed variables of the ball shear testing are also investigated in this study. The x-section technology was applied in this experiment for examining the bump shape after finishing the bumping process. In this study, we also utilize the noncontact laser technology to examine the bump height after solder bumping process. In order to understand data about SMT application of 40-mil PBGA, the solder joint height with different solder ball diameter and the reliability test data were both included in this experiment. Of course, we design a test board with daisy chain and utilize the x-section technology to achieve the jobs.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131138227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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