{"title":"低成本焊料倒装芯片","authors":"G. Rinne, P. Magill","doi":"10.1109/ISAPM.1997.581270","DOIUrl":null,"url":null,"abstract":"Since the advent of flip chip packaging technology in the solid logic technology (SLT) of IBM in the early 1960s, a great deal of thought and energy has been invested toward making flip chip cost competitive with wirebonding. While this goal has been occasionally met in the intervening years, the relentless progress of wirebond technology has repeatedly regained the advantage.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low cost solder flip chip\",\"authors\":\"G. Rinne, P. Magill\",\"doi\":\"10.1109/ISAPM.1997.581270\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Since the advent of flip chip packaging technology in the solid logic technology (SLT) of IBM in the early 1960s, a great deal of thought and energy has been invested toward making flip chip cost competitive with wirebonding. While this goal has been occasionally met in the intervening years, the relentless progress of wirebond technology has repeatedly regained the advantage.\",\"PeriodicalId\":248825,\"journal\":{\"name\":\"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISAPM.1997.581270\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISAPM.1997.581270","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Since the advent of flip chip packaging technology in the solid logic technology (SLT) of IBM in the early 1960s, a great deal of thought and energy has been invested toward making flip chip cost competitive with wirebonding. While this goal has been occasionally met in the intervening years, the relentless progress of wirebond technology has repeatedly regained the advantage.