{"title":"Adhesive and conductive adhesive flip chip bonding","authors":"R. Zenner, G. Connell, J. Gerber","doi":"10.1109/ISAPM.1997.581272","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581272","url":null,"abstract":"Over the past decade the use of adhesives for electronic interconnect has been driven by the explosive growth of flat panel liquid crystal displays (LCD). Developed and used primarily by Japanese manufacturers of consumer products, particle-loaded adhesive films fulfilled a need in LCDs that could not be met by solder reflow: low temperature, high line density (to 50 /spl mu/m pitch) electrical interconnect to indium tin oxide (ITO) traces on glass. Adhesives may also be used for flip-chip assembly. The advantages of flip-chip attach technology are the same for solder or adhesive technology: footprint reduction, low interconnect resistance, short signal line length, and elimination of single-chip packaging costs. Lower parasitics decrease rise times and decrease power requirements. To prevent differential thermal expansion induced solder fatigue, flip-chip attachment using solder reflow requires the use of an underfill adhesive applied in a separate time-consuming process. Adhesive films described in this paper inherently provide an underfill, serve as environmental protection for the chip face, as well as make a solderless electrical connection. Performance results for fine pitch chips have shown stable interconnect resistance below 10 m/spl Omega/ for bumped chip applications and approximately 100 m/spl Omega/ with unbumped chip test vehicles. The adhesive flip-chip bonding process and environmental stress results will be presented in this paper.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124523873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Schubert, R. Dudek, B. Michel, H. Reichl, H. Jiang
{"title":"Materials mechanics and mechanical reliability of flip chip assemblies on organic substrates","authors":"A. Schubert, R. Dudek, B. Michel, H. Reichl, H. Jiang","doi":"10.1109/ISAPM.1997.581268","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581268","url":null,"abstract":"This paper demonstrates a combined approach of numerical analysis and experimental investigations to study the mechanical reliability of flip chip solder joints. The effect of various design parameters like bump geometry, \"soft\" and \"hard\" underfill, and used solder mask on the thermal fatigue life of solder joints is discussed. Since special attention has been directed towards Flip Chip on Board (FCOB) assemblies, constitutive properties of polymeric and solder materials are discussed in detail. The solder is modeled using a nonlinear constitutive law with time dependent (creep) and time independent plastic strains. Furthermore, material testing shows that the underfill and solder mask materials might be considered as linear viscoelastic with temperature time shift properties. Thermal mismatch between the materials assembled is often the main reason for thermally induced stresses. Thermal cycling (125/spl deg/C...-55/spl deg/C...125/spl deg/C) is therefore the load generally used in the 3D non-linear finite element analysis. Calculation results of the solder bump deformation due to temperature changes are accompanied by experimental deformation analysis. The used MicroDAC method is based on algorithms of local object tracking in images obtained from electron scanning microscopy. The measured deformation fields were utilized for proper materials selection and processing, as well as for verification of finite element analysis.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125590722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S.M. Raid, W. Su, I. Salama, A. Elshabini-Riad, M. Rachlin, W. Baker, J. Perdue
{"title":"Plastic packaging modeling and characterization at RF/microwave frequencies","authors":"S.M. Raid, W. Su, I. Salama, A. Elshabini-Riad, M. Rachlin, W. Baker, J. Perdue","doi":"10.1109/ISAPM.1997.581280","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581280","url":null,"abstract":"Summary form only given. At high frequencies, material properties and properties of signal lines/interconnects are equally important. Thus, the present study deals with material (molding compound) characterization and modeling and characterization of lead frames and bond wires. While the microwave characterization of molding compounds can be utilized in a variety of plastic package structures, the objective of the modeling was to develop an electrical model of the 16 lead SOIC plastic package, which is popular for packaging wireless RFICs. The developed models have been successfully used by ITT GTC in developing a new generation of power amplifier RFICs. Measurement results, error analysis, and time domain package modeling techniques are presented.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114696396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Kola, M. Lau, S. Dueñas, H. Kumagai, P.R. Smith, R. Frye, K. Tai, P. Sullivan
{"title":"Thin film resistors and capacitors for advanced packaging","authors":"R. Kola, M. Lau, S. Dueñas, H. Kumagai, P.R. Smith, R. Frye, K. Tai, P. Sullivan","doi":"10.1109/ISAPM.1997.581260","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581260","url":null,"abstract":"Integrated passive components are important for high frequency hybrid microelectronics. We have fabricated resistors using reactively sputtered TaN/sub x/ (x<0.5) and Ta/sub 2/Si thin films. We report on the resistivity, temperature coefficient of resistance (TCR), microstructure, composition, and thermal stability as a function of deposition conditions. The resistivity can be tuned, for example, by varying the nitrogen concentration. We have also fabricated capacitors with high capacitance density (70 nF/cm/sup 2/) using Ta/sub 2/O/sub 5/ dielectric films. The Ta/sub 2/O/sub 5/ dielectric films were prepared by various methods such as reactively sputtered Ta/sub 2/O/sub 5/, anodization of reactively sputtered TaN,, and anodization of Ta,Si films. We report on the capacitance density, leakage current, breakdown voltage, and dissipation factor up to high frequencies. We also report on the temperature coefficient of capacitance (TCC) and thermal stability of these capacitors during subsequent processing. A variety of analytical techniques were used to characterize the film properties. These anodic Ta/sub 2/O/sub 5/ capacitors have exceptionally low leakage currents (<1 nA/cm/sup 2/ at 10 V), high breakdown fields (>4 MV/rm), and high capacitance densities (70 nF/cm/sup 2/). The ac measurements of the capacitors showed ideal behavior up to 10 MHz Generally, anodic capacitors degrade upon subsequent processing above 200/spl deg/C due to dielectric and electrode metal interaction. By engineering the dielectric and the electrode materials, we have fabricated anodic Ta/sub 2/O/sub 5/ capacitors that are stable up to 350/spl deg/C with excellent capacitor properties. These capacitors are useful as integrated passive components for advanced packaging applications.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130142044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thin film passive components integrated into silicon based multi-chip modules for aerospace applications","authors":"N. Kim, K. Coates, C. Chien, M. Tanielian","doi":"10.1109/ISAPM.1997.581262","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581262","url":null,"abstract":"Research and development activities of Boeing embedded passive technologies are described with an emphasis on resistors and capacitors. Both resistor and capacitor technologies are based on thin film processing to be compatible with the current fabrication process for silicon based multi-chip modules. Resistor material systems with two different ranges of resistivity were developed. Candidate materials included TaN/sub x/ for low resistivity and various cermet materials for high resistivity materials. Three different materials systems are being evaluated for embedded capacitors. Single or multi-layer capacitors using SiN/sub x/, and Ta/sub 2/O/sub 5/ based thin film as dielectric are being developed while only a limited study is planned on high permittivity materials. A conceptual process flow for the multi-layering scheme was developed and is being implemented with candidate capacitor materials. This paper will describe experimental results collected along this study.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115630941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Al/SiC for power electronics packaging","authors":"M. K. Premkumar","doi":"10.1109/ISAPM.1997.581284","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581284","url":null,"abstract":"Al/SiC composites have a CTE that very closely matches ceramics along with a high thermal conductivity. In addition, these composites also have an elastic modulus that is 2/spl times/ that of Cu and a density that is 66% less than that of Cu. These properties allow for a package design that is significantly superior to the traditional Cu baseplate design. This presentation discusses the unique properties of Al/SiC as it applies to power electronics packaging. The results of thermal cycling and other reliability testing of Al/SiC products are presented and discussed.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115918317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Development of low loop, long length, hydrostatically extruded bonding wire","authors":"H. Lichtenberger, Gabriel Toea, Michael Zasowski","doi":"10.1109/ISAPM.1997.581273","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581273","url":null,"abstract":"Recent developments in the microelectronics field have led to an increasing need for low loop and long length Bonding Wires. In order to develop a product to meet these needs, we have investigated the effects of Be, Cu, Ag, Ca, Pt and Al additions to high purity 5Ns gold in conjunction with a hydrostatic wire extrusion process. Bonding wire break loads and recrystallization temperatures are plotted for varying levels of these dopants. Low loop and long length Gold bonding wire is achieved by optimizing the chemistry for high recrystallization temperature and strength.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124667685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Flex on cap-solder paste bumping","authors":"P. Elenius","doi":"10.1109/ISAPM.1997.581271","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581271","url":null,"abstract":"Soldered flip chips require the formation of a solder bump on the semiconductor device. Traditional solder deposition methods of evaporation and plating have limitations both from a cost structure as well as in capability to meet product requirements. Presented in this paper are the capabilities and reliability results of the FOC (Flex on Cap) solder paste bumping process developed by Delco Electronics and practised by flip chip technologies. This paper describes the fine pitch capabilities, solder alloys, bump height uniformity, alloy control and reliability data for the FOC process. The solder paste process permits cost effective bumping of low alpha solders either W/Pb or Pb free alloys. The importance of the UBM (Under Bump Metalization) for reliable eutectic Pb/Sn and other high Sn content solders that are important for the DCA (Direct Chip Attach) market is shown. The system level cost savings of having all the necessary solder present on the IC, eliminating the deposition of solder on the board, are given.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127143042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Nguyen, D. Tracy, A. Chen, R. Giberti, J. Hatch, J. DeRosa, B. Werner
{"title":"Cost/performance analysis for plastic package \"ruggedization\" and thermal enhancement","authors":"L. Nguyen, D. Tracy, A. Chen, R. Giberti, J. Hatch, J. DeRosa, B. Werner","doi":"10.1109/ISAPM.1997.581264","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581264","url":null,"abstract":"The Plastic Packaging Consortium (PPC), a Technology Reinvestment Project (TRP) funded by DARPA under SOL 94-27 addresses the needs required to build up and strengthen an on-shore infrastructure for \"ruggedized\", thermally enhanced and high density low-cost plastic packages. The PPC is now in the second year of a two-year program. A number of technical advances has been made in various areas related to the materials of construction of the packages. However, such advances typically come at higher costs. The intention of the Program is to identify the various combinations of such advances so that the total cost of ownership would be reduced even though individual elements of the package may incur higher costs. This talk will discuss the cost/performance analysis for two arms under evaluation by the PPC, namely, package \"ruggedization\" and package \"thermal enhancement.\" \"Ruggedization\" refers to the strengthening of the plastic package to withstand the rigor of surface mounting without the need for dry bagging and baking the parts to avoid popcorning. \"Thermal enhancement\" refers to the need for higher heat dissipation without resorting to external heat sinks. SEMATECH's Cost Resources Model (CRM) was used to analyze the process flows involved for these two Focus Areas. The cost of ownership for the various combinations of package enhancement will be discussed with respect to the performance level achieved. IBIS Associates's Technical Cost Model (TCM) was applied for the flow of handling moisture sensitive devices at the board assembly level.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130410812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"New material technology for high density interconnections","authors":"D.D. Johnson","doi":"10.1109/ISAPM.1997.581247","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581247","url":null,"abstract":"A new technology is discussed that allows for the efficient interconnection of Surface Mounted Components (SMC) to high density substrates. This technology is based on the selective through metalization of porous, expanded polytetrafluoroethylene (ePTFE) membranes using a photoimaging process. The selective metalized membrane can be coated or filled with resins or adhesives to yield an Anisotropic Z-Axis Interface.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125355454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}