Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces最新文献

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Corrosion resistant wire for small diameter wire bonding applications 用于小直径焊丝粘接的耐腐蚀焊丝
M. Mckeown
{"title":"Corrosion resistant wire for small diameter wire bonding applications","authors":"M. Mckeown","doi":"10.1109/ISAPM.1997.581267","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581267","url":null,"abstract":"Wire bonding is now a major method of interconnection. Over the years, as electronic packages became more technologically advanced, the wire bonders and the wire had to mature at the same rate. Aluminum wire is one of the main components used in wire bonding these electronic devices. In some applications, this aluminum wire must be able to withstand harsh environments, such as salt spray and autoclave, within a temperature range from -40 to +125/spl deg/C. There was now a need for a wire that would be able to withstand this temperature range and withstand the harsh environment. Wire manufacturers responded by developing an anti-corrosion wire that would withstand the autoclave (pressure cooker) conditions. This aluminum based wire has been used in the larger diameter sizes (127 to 508 microns or 5 to 20 mils) for a few years already in mostly automotive applications. Recently many end-users have utilized this corrosion resistant wire in small diameter applications (50.8 and 76.2 microns or 2 and 3 mils). Most of these applications are also automotive related. Corrosion resistant wire is unique in that there are some essential dopants in the wire that prevent the wire from physical damage. This paper will discuss the composition of this type of wire and review findings from the autoclave test done on various wire types.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128801951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Microwave characterization of thin film materials for interconnections of advanced packaging 先进封装互连用薄膜材料的微波特性研究
B. Fléchet, R. Salik, J. W. Tao, G. Angénieux
{"title":"Microwave characterization of thin film materials for interconnections of advanced packaging","authors":"B. Fléchet, R. Salik, J. W. Tao, G. Angénieux","doi":"10.1109/ISAPM.1997.581278","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581278","url":null,"abstract":"Low permittivity insulator layers made of new organic or inorganic materials, associated to conductive layers, with thickness less than one micrometer are used more and more to develop interconnections of microwave or high speed circuits, and electronic packaging. Such thin film microstrip lines have been modeled between 1 GHz and 40 GHz using a rigorous full-wave method based on a modified transverse resonance technique. Comparison between theoretical and experimental propagation constants enables us to extract the in-situ complex permittivity of insulators and the electrical conductivity of conductors by an iterative optimization technique.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123919640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Passive optical alignment methods 无源光学对准方法
R. Boudreau
{"title":"Passive optical alignment methods","authors":"R. Boudreau","doi":"10.1109/ISAPM.1997.581290","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581290","url":null,"abstract":"Passive optical alignment is a new optical packaging approach for the purpose of optical fiber attachment in components. It was developed in order to address the high cost associated with the traditional active optical alignment method. The basic difference between the methods is that for the active alignment methods it is necessary to operate the unit during the assembly and packaging process of fiber attach while for the passive alignment method it is not.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123156353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An ovenview of SBU (Sequential Build-Up)/Microvia technologies? SBU(顺序积聚)/微孔技术概述?
I. Ho
{"title":"An ovenview of SBU (Sequential Build-Up)/Microvia technologies?","authors":"I. Ho","doi":"10.1109/ISAPM.1997.581245","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581245","url":null,"abstract":"Driven primarily by portable computers and wireless communications, today's electronics continuously demands smaller, lighter, faster and yet lower cost packaging. In order to support future needs, PWBs are expected to accommodate high I/O fine-pitch devices as well as small foot-print area-array packages such as chip-size packages (CSP), flip-chip attach (FCA) and direct-chip attach (DCA). Furthermore, the laminate-based substrates will also be used for IC packaging, replacing costly ceramic-based substrates. Providing high-density interconnection (HDI) with blind/buried vias at low cost, SBU technology has overcome the cost issues associated with small hole drilling and sequential lamination. Furthermore, the technology holds promise in reducing layer count and board size and allows greater packaging efficiency. In the last two years, the technology has drawn heavy attention from OEMs and PWB manufacturers worldwide. Many process alternatives are under development. Although the technology is at its infancy, leading processes are emerging.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124632085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Reduced cycle time epoxies for flip chip underfill 减少倒装芯片底填料环氧树脂的循环时间
M. Bonneau, J. Stewart
{"title":"Reduced cycle time epoxies for flip chip underfill","authors":"M. Bonneau, J. Stewart","doi":"10.1109/ISAPM.1997.581256","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581256","url":null,"abstract":"The further development of the epoxy flip chip underfill encapsulant material has been demonstrated as necessary to enhance the temperature cycle performance of the solder ball connections. A reduction of the epoxy encapsulant under fill processing and cure time is needed in order to better fit into the production line environment. This paper reports and discusses the improvement of under fill flow speed and distance, the various material properties such as resin viscosity, filler effects and the overall rheology with respect to under fill flow. The reduction of oven cure time is a key requirement for faster \"throughput\" and reduction of \"work in process\". The minimum cure times needed in order to maintain the level of reliability required as a flip chip under fill material are discussed. Physical material properties of these flip chip materials such as; glass transition temperature, coefficient of thermal expansion, tensile modulus, and adhesion are discussed in relation to reliability performance.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125658373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Microwave characterization of packaging materials 包装材料的微波特性
D. Amey, S. Horowitz
{"title":"Microwave characterization of packaging materials","authors":"D. Amey, S. Horowitz","doi":"10.1109/ISAPM.1997.581283","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581283","url":null,"abstract":"A major test program to characterize advanced interconnection materials in the 1 to 20 GHz range was initiated. The material systems which were tested include a variety of new Thick Film and Low Temperature Cofired Ceramic (LTCC) dielectrics as well as alumina dielectrics. Gold and silver conductors were applied using conventional screen printing and the new FODELB photopatterning techniques. Thin film conductors on 96% Aluminia and copper clad FR-4, Polyimide, BT and PTFE printed wiring materials were also characterized as benchmarks. The presentation discusses the key attributes of each technology, the test method and data which shows that conventional Thick Film Materials exhibit good uniform properties suitable for applications in the 7+ GHz range and that LTCC Green Tape/sup TM/ and photopatterned FODELB Thick Film materials significantly extend the operating frequency range of ceramic materials exhibiting performance previously only achievable with Thin Film and high performance printed wiring materials.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"355 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131729778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Microvia materials: enablers for high density interconnects 微孔材料:实现高密度互连
J. Paulus, M. Petti
{"title":"Microvia materials: enablers for high density interconnects","authors":"J. Paulus, M. Petti","doi":"10.1109/ISAPM.1997.581248","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581248","url":null,"abstract":"As new printed circuit board fabrication processes evolve to build high density suppliers are developing compatible with these processes. This paper will discuss laser and plasma ablatable dielectric materials, available as thin films or coatings on copper. These materials are compatible with conventional PWB techniques, (e.g. layup, lamination, DES) and are amenable to mass blind via formation methodologies. With component densities increasing year after year, the need for dense, cost-effective PWB solutions is immediate. The additional demand for solutions in the same or smaller footprint, at equivalent or lower layer count increases the complexity of the problem. Both of these needs are met when large numbers of small vias are rapidly formed, by laser or plasma ablation techniques, in these dielectrics, connecting outerlayer circuitry to very dense innerlayers, laden with buried vias and fine lines and spaces. These microvia materials play a key role in the industry's ability to produce high density interconnect solutions.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122744381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
High performance underfills for low-cost flip-chip applications 用于低成本倒装芯片应用的高性能填充物
S. Shi, G. Jefferson, C. Wong
{"title":"High performance underfills for low-cost flip-chip applications","authors":"S. Shi, G. Jefferson, C. Wong","doi":"10.1109/ISAPM.1997.581251","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581251","url":null,"abstract":"To develop the no-flow underfill materials suitable for no-flow underfill processing for flip-chip solder joint interconnects, we studied several catalysts for epoxy/anhydride base no-flow underfill formulations. These catalysts include metal acetylacetonates and imidazolium salts and were found to be potential candidates for no-flow underfill applications based on the curing profile of the formulations, glass transition temperature (Tg), and coefficient of thermal expansion (CTE) of the cured formulations. The added amount of catalyst and hardener has separate effects on curing reaction peak temperature of the prepared formulations, Tg, and CTE of the cured formulations. The added concentration of catalyst mainly affects the curing reaction peak temperature, but has little effect on the Tg and CTE of the cured formulations. The added concentration of hardener mainly affects the Tg and CTE of the cured formulations, but has little effect on the curing reaction peak temperature of these formulations. Water molecule complexed with metal ions in metal acetylacetonates can be released by heating which consequently shifts the curing reaction peak to lower temperatures by several decades of degrees. The curing profile and the correlation between the curing reaction peak temperature as latent catalysts for epoxy/anhydride resins and their decomposition temperature suggests that the decomposition fragments are most likely the active species responsible for initiating polymerization in epoxy/anhydride resin systems.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122750310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Ball bumping and coining operations for TAB and Flip Chip 球碰撞和铸造操作的TAB和倒装芯片
L. Levine
{"title":"Ball bumping and coining operations for TAB and Flip Chip","authors":"L. Levine","doi":"10.1109/ISAPM.1997.581269","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581269","url":null,"abstract":"The process of using a ball bonder to form bumps on a chip, for subsequent TAB or Flip Chip attachment to a substrate, has now reached the production stage. A number of companies are using the process for full scale production. Other companies are using the process for rapid prototyping and limited quantity production. It requires no masks, uses existing equipment, and in many cases provides the most cost effective method for depositing bumps on chips. Two process variations are prevalent. 1. Bumping and coining, is a process where a normal ball bond with a short ductile fracture tip protruding from the top of the ball is bonded to the device, then coined flat by a second stage operation. 2. The stud bumping process produces a short loop and the crescent bond is placed on the shoulder of the ball.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"40 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114037643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Embedding technology-a chip-first approach using BCB 嵌入技术——采用BCB的芯片优先方法
M. Topper, K. Buschick, J. Wolf, V. Glaw, R. Hahn, A. Dabek, O. Ehrmann, H. Reichl
{"title":"Embedding technology-a chip-first approach using BCB","authors":"M. Topper, K. Buschick, J. Wolf, V. Glaw, R. Hahn, A. Dabek, O. Ehrmann, H. Reichl","doi":"10.1109/ISAPM.1997.581243","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581243","url":null,"abstract":"With the current trend to ever faster clock rates the propagation delays between the chips constitute a significant portion of the clock cycle. Mounting both active and passive devices as closely together as possible will therefore boost system's performance. Although flip-chipped devices have good performance, design constraints may prevent the placement of pads to comply with flip chip design rules. An additional advantage of the embedding technology is the possibility to employ 3-D stacking, the highest package density. Bare dice and standard passive components were embedded into a ceramic substrate to achieve a common, planar surface. Hence by employing thin-film processing all components can be directly interconnected to the copper routing of the module. Benzocylobutene (BCB) with its low curing temperature is preferred as dielectrical polymer for the embedding technology. Application of bonding or soldering techniques which might limit the reliability is avoided. This offers excellent electrical properties of the wiring system. By planarizing the reverse side of the MCM a low thermal resistance between heat sink and dice can be accomplished simultaneously for all embedded components. An SRAM MCM and a Thermotest MCM demonstrate the facibility of the embedding technology.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124092396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
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