Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces最新文献_第3页

Computational fluid dynamic and heat transfer analysis of an Al/SiC IGBT power hybrid package Al/SiC IGBT功率混合封装计算流体力学及传热分析

Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces Pub Date : 1997-03-09 DOI: 10.1109/ISAPM.1997.581286

J. Fusaro, P. Rodriguez

{"title":"Computational fluid dynamic and heat transfer analysis of an Al/SiC IGBT power hybrid package","authors":"J. Fusaro, P. Rodriguez","doi":"10.1109/ISAPM.1997.581286","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581286","url":null,"abstract":"This paper describes the fluid dynamic and heat transfer optimization of an integrally cooled Aluminum and Silicon Carbide (Al/SiC) high current power hybrid package. Discussed herein are the design and supporting analyses for a module, suitable for electric power-train applications. These modules are constructed with insulated gate bipolar transistors (IGBT) and free wheeling diodes arranged in selected circuitry, supporting 3 phase motor control. Aluminum Silicon Carbide has evolved as a heat sink material of choice for certain high power hybrid packages. The ability to net shape cast Al/SiC allows for increased integration of the power stage heat exchanger with the package itself. Improved thermal management, increased power density, reduced weight and lower cost were all motivating factors for this work. The study, conducted at Motorola's Power Products Division indicates that heatsink designs and internal flow geometry's play a critical role in equalizing device junction temperatures. The study has shown that heatsink configurations exist that have minimal dependence on die placement, thus allowing for greater circuit flexibility. Results of three dimensional finite volume coupled-field computational fluid dynamic (CFD) and finite difference heat transfer analyses will be presented.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131025414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Thermomechanical stresses in an underfilled flip chip DCA 未填充倒装芯片DCA中的热机械应力

Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces Pub Date : 1997-03-09 DOI: 10.1109/ISAPM.1997.581275

C. Le Gall, J. Qu, D. McDowell

{"title":"Thermomechanical stresses in an underfilled flip chip DCA","authors":"C. Le Gall, J. Qu, D. McDowell","doi":"10.1109/ISAPM.1997.581275","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581275","url":null,"abstract":"Flip chip interconnection technology has recently been extended to direct chip attach (DCA) to organic printed wiring boards (PWBs). However, the coefficient of thermal expansion (CTE) of the PWB is almost an order of magnitude greater than that of the silicon die; under operating conditions, this mismatch subjects the solder joints to cyclic stresses, which may result in mechanical fatigue failure of the solder connections. Such CTE mismatch-induced stresses, manifested by the increasing die size and temperature excursions, have posted a great challenge to the thermomechanical reliability of flip-chip DCA packages. To prevent premature thermomechanical failure and ensure the reliability of a DCA package, the thermomechanical stresses caused by the CTE mismatch, which is the driving force to failure, must be understood. Furthermore, design and processing technologies must be developed to minimize such stresses. In this paper, a general methodology is developed to conduct stress analysis in flip-chip DCA with underfill encapsulation using the finite element method. In particular, two fundamental issues are addressed, namely, effects of die size on the stress fields and the optimization of thermomechanical properties of underfill materials. It is shown in this paper that the nature of stress fields in underfilled flip chips is fundamentally different from that in any other surface mount assemblies. The distance to neutral point (DNP) is no longer a dominant factor in determining the magnitude of the stresses in underfilled flip-chip packages. Consequently, as far as the stresses are concerned, the die size is not a limiting factor. The underfill optimization studies have demonstrated that both stress and strain fields should be considered in the analysis of a flip chip assembly. Some general guidelines have been provided for selecting optimal CTE and modulus values which minimize stress and strain fields in the solder and silicon chip.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134264797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Self-reinforced dielectric substrates based on PIBO film 基于PIBO薄膜的自增强介质基板

Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces Pub Date : 1997-03-09 DOI: 10.1109/ISAPM.1997.581242

D. A. Dalman, W. Hwang, W. J. Harris, L. Lopez, C. Murphy

{"title":"Self-reinforced dielectric substrates based on PIBO film","authors":"D. A. Dalman, W. Hwang, W. J. Harris, L. Lopez, C. Murphy","doi":"10.1109/ISAPM.1997.581242","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581242","url":null,"abstract":"Consumer electronics products in applications including mobile communications, work stations, small computers, automotive controls, and even high temperature, high reliability but less cost sensitive applications in military, space and aerospace, are moving relentlessly toward smaller, thinner and lighter formats in less costly packages. Interconnect (attachment pad) density requirements in these products are rapidly outstripping the density achievable through fabrication of traditional multilayer printed wiring boards (PWBs) derived from currently available materials. Reinforced dielectric substrates for PWBs (whether woven or non-woven and regardless of resin Tg) are reaching limits of utility for state of the art electronics. Build-up of dielectric layers on traditional PWBs utilizing photo, laser or plasma formed mass vias with small pads is one of the few approaches capable of achieving the desired functionality of leading edge products, even though a substantial cost penalty is incurred. A second way to increase routing density by creation of smaller pads is through the use of new cost effective dimensionally stable laminates. Dielectric film substrates which are thin, self-reinforced and have a high degree of in-plane isotropic dimensional stability are in development. These materials could provide for small vias and capture pads while utilizing the economics of large panel (18\" by 24\") fabrication. Copper clad panels and associated bond-ply adhesives based on polyimidebenzoxazole (PIBO) film will provide that capability.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127604373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Vertical interconnect in multilayer applications using Ormet/sup R/ conductive composites 使用Ormet/sup /导电复合材料的多层应用中的垂直互连

Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces Pub Date : 1997-03-09 DOI: 10.1109/ISAPM.1997.581249

C. Gallagher, G. Matijasevic, P. Gandhi, D. Pommer, S. Sargeant, R. Kumar, D. Neuburger

{"title":"Vertical interconnect in multilayer applications using Ormet/sup R/ conductive composites","authors":"C. Gallagher, G. Matijasevic, P. Gandhi, D. Pommer, S. Sargeant, R. Kumar, D. Neuburger","doi":"10.1109/ISAPM.1997.581249","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581249","url":null,"abstract":"Lamination of circuit layer pairs for multilayer constructions requires an innovative strategy for vertical interconnect in order to achieve high density. Multilayer circuits can be achieved by laminating circuit pairs with the use of an appropriate dielectric bond-ply. Circuit pairs are made of a high performance material with predrilled and plated vias and a pair of copper layers for defining circuitry. Vertical interconnect has been achieved by integrating patterned conductive vias with the bond-ply. The patterning of the bond-ply is achieved using a high speed lasing system. The conductive material interconnection can be made in several ways including patterning directly onto the circuit as well as filling the lased holes in the bond-ply. This presentation will discuss the results of work done using a conductive ink material for vertical interconnect. This organic-metallic (Ormet/sup R/) composite, which is based on transient liquid phase sintering, is used to make a connection between the two pads by alloying with the pad metallization. The partially sintered network also extends through the via interconnect providing a reliable network for electrical conduction. Six layer structures composed of three circuit layer pairs and two via interconnect layers have been manufactured. Good electrical connection has been achieved by connecting 5 mil pads vertically. Cross-sectional examination demonstrates a continuous metal network. Preliminary reliability testing indicates that the connections are electrically and mechanically robust.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131516028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Single mask stress buffer 单掩膜应力缓冲

Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces Pub Date : 1997-03-09 DOI: 10.1109/ISAPM.1997.581244

B. Rogers, D. Scheck, P. Garrou

{"title":"Single mask stress buffer","authors":"B. Rogers, D. Scheck, P. Garrou","doi":"10.1109/ISAPM.1997.581244","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581244","url":null,"abstract":"Large die such as SRAMs and DRAMs are subject to significant stress resulting from thermal expansion mismatch of the die and packaging materials. The use of polymers as stress buffering media has been widely practiced to increase the reliability of these devices. Many of these devices require that small windows (/spl les/10 /spl mu/m) be opened up in the polymer over \"fuse links\" which are used to reroute or reconfigure inactive circuits. The need for tighter resolution in the stress buffering layer, as well as the desire for shorter process cycle times, has moved the industry from wet etch to photosensitive materials. Photosensitive BCB (Cyclotene) has been widely reported for use as a dielectric in numerous advanced packaging applications. A one mask photo-BCB stress buffer process has also been reported for opening up bond pads and fuse links in underlying SiN die passivation. Traditional passivation/stress buffer processing has required masking and dry etching of the SST followed by coating and patterning of the polymer dielectric (two mask process). The reduction in processing steps and processing time using the one mask BCB process can significantly lower the cost of ownership for passivation/stress buffer layers.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131561863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Materials issues for solutions of Power Electronic Building Blocks (PEBB) 电力电子模块(PEBB)解决方案的材料问题

Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces Pub Date : 1997-03-09 DOI: 10.1109/ISAPM.1997.581288

A. Lostetter, J. Webster, R. Hoagland, F. Barlow, A. Elshabini-Riad, A. Nelson

引用次数: 5

The effect of substrate materials on the thermo-mechanical behavior of multilayered structures 衬底材料对多层结构热力学行为的影响

Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces Pub Date : 1997-03-09 DOI: 10.1109/ISAPM.1997.581277

R. Dunne, S. Sitaraman

引用次数: 2

Microwave characterization of low temperature cofired ceramic system 低温共烧陶瓷体系的微波表征

Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces Pub Date : 1997-03-09 DOI: 10.1109/ISAPM.1997.581282

S. Vasudevan, A. Shaikh

{"title":"Microwave characterization of low temperature cofired ceramic system","authors":"S. Vasudevan, A. Shaikh","doi":"10.1109/ISAPM.1997.581282","DOIUrl":"https://doi.org/10.1109/ISAPM.1997.581282","url":null,"abstract":"Low Temperature Cofired Ceramic (LTCC) is a multilayer electronic packaging technology and has a unique ability to integrate passive components such as resistors, capacitors and inductors in a monolithic package. The LTCC can be used to make electronic circuits with high density interconnects and complex shape buried components. LTCC Technology has been extensively explored in the microelectronics industry as a ceramic packaging technology for integrated microcircuits. Ferro's A6 tape has a dielectric constant of 6 and low microwave losses of <0.17 dB/in at 10 GHz. The high frequency (GHz range) audio and video transmission application is expected to expand very rapidly in the near future. Microelectronic packages for high frequency application require conductive materials with high conductivity and dielectrics with low losses at microwave frequency range. The objective of the paper is to characterize the Ferro A6 LTCC system in the microwave frequency range. Ring resonator designs were used to characterize microwave properties of A6 LTCC packages with Ag, Au and Ag, Au mixed conductor systems. The effect of processing parameters such as peak firing temperature and time on microwave characteristics of LTCC system was studied. The effect of processing parameters on Q factor and microwave losses were studied and presented. The effect of conductor type and its surface roughness on microwave properties is also presented.","PeriodicalId":248825,"journal":{"name":"Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114988730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Imp act of MCM technology on high speed transient waveforms MCM技术对高速瞬态波形的影响

Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces Pub Date : 1997-03-09 DOI: 10.1109/ISAPM.1997.581281

R. Wenzel, D. Keezer

引用次数: 2

Built-in passive components in multilayer ceramics for wireless applications 用于无线应用的多层陶瓷内置无源元件

Proceedings 3rd International Symposium on Advanced Packaging Materials Processes, Properties and Interfaces Pub Date : 1997-03-09 DOI: 10.1109/ISAPM.1997.581261

C. Nelson, R. Sigliano, C. Makihara

引用次数: 5