An ovenview of SBU (Sequential Build-Up)/Microvia technologies?

Abstract

Driven primarily by portable computers and wireless communications, today's electronics continuously demands smaller, lighter, faster and yet lower cost packaging. In order to support future needs, PWBs are expected to accommodate high I/O fine-pitch devices as well as small foot-print area-array packages such as chip-size packages (CSP), flip-chip attach (FCA) and direct-chip attach (DCA). Furthermore, the laminate-based substrates will also be used for IC packaging, replacing costly ceramic-based substrates. Providing high-density interconnection (HDI) with blind/buried vias at low cost, SBU technology has overcome the cost issues associated with small hole drilling and sequential lamination. Furthermore, the technology holds promise in reducing layer count and board size and allows greater packaging efficiency. In the last two years, the technology has drawn heavy attention from OEMs and PWB manufacturers worldwide. Many process alternatives are under development. Although the technology is at its infancy, leading processes are emerging.