Advanced encapsulation processing for low cost electronics assembly-a cost analysis

Abstract

Major cost driving factors for current advanced electronics assembly processes are polymer encapsulation and polymer dispensing processing. This is particularly true for flip chip on board interconnection technology. As an integral part of the Low Cost Next Generation Flip Chip Processing Program of Georgia Tech's Packaging Research Center, a preliminary industry benchmark study has been conducted to determine high cost process characteristics of state-of-the-art flip chip assembly technology. The benchmarking analysis has identified certain steps of the assembly process as high cost including bumping, underfill dispensing and curing of underfill material. Based on these cost factors, a new flip chip assembly process concept has been developed to reduce process steps, process time, and cost. A cost model has been created to analyze the new assembly process and compare it with current benchmark processes. Leveraging the cost analysis, further cost reducing refinements to the process have been identified achieving a low cost solution. The work presented will focus on flip chip assembly cost analysis and process design.