2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Comprehensive Study on the Encapsulation for the Intelligent Power Module","authors":"S. Lim, Eva Wai Leong Ching, Kazunori Yamamoto, T. Yue","doi":"10.1109/EPTC47984.2019.9026628","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026628","url":null,"abstract":"With the increasing demand of compact and high power rated power module in the EV / HEV (Electric Vehicle / Hybrid Electric Vehicle) industry, packaging of power module is getting more challenging. The push for intelligent power modules in the dynamic markets has led to continuous innovations and material enhancements, as well a lot of R&D investment. Devices which are able to work in the higher temperature and switching at a higher frequency are required [1]–[3]. In this paper, we evaluated six types of molding compound to study their effects of small gaps filling capability and package warpage during the assembly process. In summary, we are able to achieve a relatively low warpage on the molded module for this WLP fabrication method.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122441000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interface Analysis of High Reliable Hermitic Sealed Microfluidic Channels for Thermal Cooling in 3D ICs","authors":"Hemanth Kumar Cheemalamarri, Satish Bonam, Dhiman Banik, S. Vanjari, S. Singh","doi":"10.1109/EPTC47984.2019.9026576","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026576","url":null,"abstract":"Thermal management is the critical issue in all present conventional 2D electronic packages, and is more crucial in the case staked dies of advanced 3D IC technology, because of increased power density and complex chip designs. The traditional methods are reaching their limits towards cooling requirement of 3D ICs. The liquid cooling micro-channel are the most attractive for high heat flux mitigation. However, the integration of such micro-channels across the stacked dies, is challenging. In this work, we are proposing a facile method of fabrication and integration of a high reliable, tight sealed inter-die microfluidic channels for 3D ICs. The integration of inter-die microchannel over three stacked layers has been developed with titanium silicide as a bonding interface by simultaneous application of optimal heat and force is matching towards CMOS compatibility. Here, we demonstrated the reaction mechanism of titanium (Ti) and importance of Ti thickness across the bonding interface. The temperature and load optimizations carried out using the surface profile of Ti using AFM before bonding, and interface inspection after bonding, by using, C-SAM and razorblade insertion. The interface reactions and thickness of Ti optimization has inspected using X-FESEM and EDS profile. After conforming void free high reliable bonding interface, at optimized conditions, we fabricated fine pitch ($200 mu mathrm{m}$) with $100 mu mathrm{m}$ width and $40 mu mathrm{m}$ depth micro-channels at inter-dies of three-layer stacked silicon structure using titanium as interlayer. Along with, we demonstrated the micro channel integration across the stacked wafers for future high performance 3D IC designs in a facile approach.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124546131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A New Type Low Cost Sandwiched Power Package Structure and its Manufacturing","authors":"Garry Ge, G. Lye, Sonder Wang, J. Zaal","doi":"10.1109/EPTC47984.2019.9026671","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026671","url":null,"abstract":"Now stacked die 3D package is much popular, especially for such power 3D package. For example, sometimes it designs control die stacking on power die; (refer to below package structure design) and control die apply thinner Cu wire bonding; but power die applies thicker Al wire bonding. This looks like conventional stacked dies design.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127635546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and Deep Explicit Model Predictive Control for Server Processor Direct Liquid Cooling","authors":"Haoran Chen, Yong Han, G. Tang, Xiaowu Zhang","doi":"10.1109/EPTC47984.2019.9026588","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026588","url":null,"abstract":"Direct liquid cooling greatly improves the capacity and efficiency for high thermal designed power (TDP) processors. Advanced micro-structured cooling devices and loop system has been designed. Given rapid changing working load condition and complex thermal dynamics of the system, advanced control method is needed to balance cooling power and energy consumption in order to improve operating efficiency. This paper presents the design and implementation of an explicit model predictive controller based on neural network for the liquid cooling system. This neural network explicitly represents the decisions in terms of observations. Loss function for training the neural network is derived from the paradigm of model predictive control, where the model is obtained from physical-empirical-hybrid simulations. The training data is sampled uniformly from the working point of the system, and training process is done on cloud with model. The well-trained model is then implemented as controller in a local experimental platform. Experiments on cooling efficiency performance under randomly varying loads show that this controller has better temperature control and reduced pump energy consumption comparing to traditional PID controller. This result achieves progress on: 1) characterizing thermodynamics of the processor liquid cooling system by simplified and approximated model; 2) building experimental platform to support testing of liquid cooling control algorithms; 3) developing an explicit form of model predictive controller approximated by deep neural network (DEMPC); and 4) demonstrating the performance of the DEMPC over the traditional proportional controller.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115226325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of Flip-Chip Solder Joints under Isothermal Vibration Loading","authors":"K. Meier, D. Leslie, A. Dasgupta, M. Roellig, K. Bock","doi":"10.1109/EPTC47984.2019.9026642","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026642","url":null,"abstract":"This work focuses on the reliability needs which are caused by the use of recent package solutions for harsh environmental use cases such as assisted or autonomous driving. Simultaneous thermal and mechanical loading of highly integrated packages as Flip-Chip (FC) packages has to be considered, investigated and understood. An earlier introduced test approach used to investigate CR0805 solder joints under combined loading was modified to enable the analysis of FC solder joints. Thus, investigations of solder joint geometries of FC, CSP and BGA packages are now possible. In this work, results on the fatigue behaviour of SnAgCu FC solder joints will be shown. The experiments were conducted under varied harmonic vibration amplitudes at room temperature. A 4.6 x 2.6 mm2 bare die FC package with a 5 x 5 interconnection grid was tested. Bump size, pad diameter and stand-off are $370 mumathrm{m}, 330 mumathrm{m}$ and $280 mumathrm{m}$, respectively. The damage and fatigue behaviour of the FC solder joints was examined using cross sections. First, test results show damage of solder joints stressed with a peak-to-peak deflection of 1.6 mm for up to 75 Million cycles at room temperature. The damage occurred within the solder volume in very close proximity to or at the substrate pad intermetallic interface. Further tests considering varied stress levels are ongoing.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"110 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115732903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of Flexible Printed Heater to Improve Uniform Heating","authors":"Z. Cen, X. Shan, B. Salam, Wai Lai Lai, B. Lok","doi":"10.1109/EPTC47984.2019.9026643","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026643","url":null,"abstract":"Because of versatile applications, heater design is important for flexible printed heaters. Trace-based printed heater, one of the commonly used flexible printed heaters, has a challenge in uniform heating. In this paper, simulations were conducted to study effects of trace width and gap on heating performance of trace-based printed heater. Heating performance can be enhanced by adjacent traces in multiple traces as compared to the case of individual trace. Such heating enhancement as well as the heating uniformity varies with trace gap. Based on the temperature profile variations with trace gap that have been found in simulations, printed heater design can be done according to the required heating uniformity. Besides the internal traces, external trace and trace edge can be adjusted to facilitate heating uniformity. Narrower external trace and trace edge can compensate the lower temperatures at heater boundaries. By choosing proper widths and gaps for internal and external traces, printed heater with good heating uniformity can be design.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115812102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comprehensive Study of Tin-Silver-Copper Lead-Free Alloys on Various Bond Pad Metallisation","authors":"N. Jaafar, C. Choong","doi":"10.1109/EPTC47984.2019.9026678","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026678","url":null,"abstract":"SnAgCu305 (SAC305) solder alloy is extensively used as solder bump interconnects in industry due to their high strength and good reliability performance. SAC305 solder bump is applicable both to 1st and 2nd level solder interconnects. It connects the chip and board together to provide the electrical connection, heat dissipation and mechanical strength to the whole package [1], [2]. Wettability of the molten solder ball onto the bonding pad is crucial. The formation of the solder ball to the bond pad will determine the electrical connections and impact the reliability results. Conventional reflow soldering process is a commonly used in the assembly packaging. It is a process which involved the flux being apply onto the metal bond pads first. Solder ball is then being place onto the metal bond pad by using stencils. Excess residues from the flux after reflow are then remove via cleaning. Hence, creating solder bumps and interconnections in the assembly packaging. This standard process which included the cleaning step may not be applicable to Optoelectronics and MEMS packaging [3]. The cleaning process can cause damage to the sensitive structures. Laser solder ball jetting technology which used a flux-less method is introduce to mitigate the handling of the fragile structures. Gold metallisation surface is an excellent bonding material for the bond pad to ensure good solder wettability. Due to cost consideration, Palladium, Platinum and Copper materials are explored as an alternative to expensive gold finishing. We will cover and study the laser solder ball jetting process comparing SAC305 solder ball onto Gold, Palladium, Platinum and Copper surface finishing. Initial results have shown that the average ball height for SAC305 with Au surface is 42.46um. The ball height for the Pd and Pt are comparable with measurement of 57.33um and 56.12 um. The ball height of SAC305 with Cu surface is the highest, with measurement of 60.28um as shown in Table 1. These prove that the Au have the best wettability as compared to the rest as shown in the Figure 7. Ball shear strength, failure mode and intermetallic growth of the SAC305 onto the Gold(Au), Palladium(Pd), Platinum(Pt) and Copper(Cu) surface finishing will be further study and discuss in the following sections.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114695122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigate for Very-Low-Voltage Test Implemented In Probe","authors":"Yan Liu, Helen Li, Albert Zheng","doi":"10.1109/EPTC47984.2019.9026635","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026635","url":null,"abstract":"Integrated circuit (IC) manufacturers perform production tests to detect defective part to guarantee the quality level of the product. Weak ICs contain flaws, defects that do not cause functional failures at some or all normal operating conditions but degrade the ICs performance, reduce noise margins, or draw excessive supply current. The current normal Low voltage test is not able to defect weak ICs or eliminate the early-life failures. The auto and military customers have very high quality requirement. Very-Low-voltage test can detect the defects (flaws) that cause early-life failures or intermittent failures. And the cost of Very-Low-Voltage test is very low. Very-Low-Voltage testing is a method where a test is performed at a supply voltage that is much lower than its nominal operating voltage. It can detect resistive shorts and delay flaws that are caused by degraded signals or diminished-drive gates. It can be implemented in die level, and no special equipment requirement of replacing the defect, which do not bring the additional cost. In this paper, the study aimed mainly at Very-Low-Voltage implemented in DC Scan test at probe level, and the core voltage value of DC scan test for different domains setup is discussed. JMP software is data analysis tool used in the study, including data comparison among DOM1, DOM2, DOM3 and ARM core. Optimized the core voltage, determining the best parameters to be used, and implemented it in probe program. Collected the real probe Very-Low-Voltage rejects and do Electric and Physical Failure Analysis(FA). For the failure unit, diagnostic, shmoo analysis between Level (VDD_SOC_CAP) and Period, Laser Assisted Device Alteration(LADA), and Soft Defect Localization(SDL) were performed on failure unit, and the anomaly was found. After the unit was thinned, Electron-Optical Probing(EOP) and cross section were performed on the anomaly location. The high resistive conduct among metal is found in FA. With the optimized data, the good probe test performance was get, and improved ICs quality. The Very-Low-Voltage test can screen out the normal low voltage rejects. The traditional normal low voltage DC Scan tests were replaced by Very-Low-Voltage DC Scan tests, which also reduce the probe test time. It is concluded that the Very-Low-Voltage test is good test method in probe to guarantee the die quality, improve the defect coverage, screen out the weak ICs, and reduce the test cost.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126725595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication of Deep Microfeatures in Glass Substrate using Electrochemical Discharge Machining for Biomedical and Microfluidic Applications","authors":"D. K. Mishra, J. Arab, Karan Pawar, P. Dixit","doi":"10.1109/EPTC47984.2019.9026714","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026714","url":null,"abstract":"Microchannels created in glass-based substrates have wide application in biomedical and microfluidics devices. Electrochemical discharge machining (ECDM) is a low cost method to fabricate microfeatures in electrically nonconductive materials such as glass, quartz, ceramic, etc. In this work, ECDM has been used to fabricate an array of microchannels in soda-lime glass substrate using a pulse power supply and 30% (wt.) KOH electrolyte. Multi-tip array tools with different configurations were used as tool electrode. Deep microchannels of different geometries i.e. straight, spiral, and, zigzag were fabricated using multi-pass micro-milling approach. The effect of pass number on the geometrical characteristics of the microchannel such as depth, width was studied. The surface quality of the fabricated microchannels was analyzed using an optical microscope. The channel depth and width showed an increasing trend with an increase in the pass number. Microchannels with smoother sidewalls and bottom surfaces were fabricated. Tool wear was found to be significant as the channel depth and the pass number was increased.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124363256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"How Much Baking Time is Needed for Moisture-Sensitive Packages?","authors":"K. Newman, Lulu Ma, R. Joshi, Xuejun Fan","doi":"10.1109/EPTC47984.2019.9026622","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026622","url":null,"abstract":"This paper proposes a new method to determine the baking time for moisture-sensitive packages prior to dry pack. The concept is based on consideration of the continuous drying process for a package within moisture barrier bags (MBB), which contain a desiccant. If the moisture is not completely dried out during bake (usually at 125°C), the residual moisture will continue to diffuse out of the package body during storage and shipment in the MBB. In this paper, a 2.5D package is used for a worst-case scenario simulation through finite element modeling. It shows that after a 24hr bake at 125°C, the residual moisture weight gain remains 13% of the total saturated weight gain, and the maximum moisture concentration remains as high as 40% of the saturated moisture concentration; however, after 4 weeks of storage at 30°C in the MBB the residual moisture weight decreases to less than 1%, and the maximum saturated moisture concentration decreases to less than 5% of the saturated moisture concentration. Depending upon package construction, storage conditions and storage time before customer opening of MBB, the modeling results show that consideration of moisture diffusion in the MBB may permit the bake schedule to be shortened.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"468 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123469305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}