2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Study on the Method to Analyze the Electrical Contact Resistances of Press-Pack IGBT devices","authors":"Xiao Wang, Hui Li, Ran Yao, Haiyang Long, Yi Zhong, Renze Yu, Jinyuan Li","doi":"10.1109/EPTC47984.2019.9026591","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026591","url":null,"abstract":"Electrical contact resistances are the link between the mechanical model and the electrical model, which should be accurately determined to analyze the electro-thermal distribution of the press-pack IGBT devices. However, determining the electrical contact resistances is very difficult because they are affected by pressure and material properties and cannot be measured directly. In this paper, a method to identify electrical contact resistances is proposed based the electrical contact theory for press-pack IGBT devices. Firstly, the mathematical model of electrical contact resistance is derived by considering contact pressure, surface roughness, surface micro-hardness and material resistivity. Then, a circuit model of single-chip press-pack IGBT device is established by using the presented electrical contact resistances. Furthermore, the surface characteristics of the materials are analyzed to determine the parameters of electrical contact resistances, especially the effects of the chip surface metal coating. Finally, the influence of pressure on the electrical contact resistance of each contact surface of the device is also analyzed. The relationship of the on-resistance of the sing-chip press-pack IGBT device with pressure is obtained by using four-point probing approach. The validity of the proposed model is demonstrated.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128469964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Water Washable Coatings for Plasma Dicing Processes","authors":"M. Day, L. Sirois, S. Erickson, Allison Gray, J. Moore","doi":"10.1109/EPTC47984.2019.9026614","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026614","url":null,"abstract":"As the dimensions of thin and tiny die trend smaller, they become candidates for laser assisted plasma singulation (LAPS), otherwise referred to as plasma dicing. The process involves creating a patterned mask whereby the plasma chemistry penetrates open areas and down into the substrate. When complete, the mask is cleaned leaving fully singulated die. Water washable coatings for mask creation are preferred. Ideally, they should exhibit high plasma resistance and be tuned for good laser interaction. Daetec's washable coatings exhibit thermal resistance over 300°C, making them the most unique materials on the market. [1] These are cast from water, processed, and removed by water. Simple spin coating achieves $< 5mu mathrm{m}$ coverage while conforming over high features is achieved by “nozzle-less” spraying with equipment designed by Ultrasonic Systems, Inc. (USI).[2] An ultrasonic head breaks the liquid into small drops to form a fine spray that deposits on faces and around corners. Once coated, substrates proceed to laser processing, tuned to delicately break through the washable layer with little or no effect to the substrate. Desired coating compositions use heat resistance, high melt viscosity, and sufficient type and amount of absorptivity for good laser engagement. These properties minimize snow-plow (“re-cast”) effects during laser patterning and further minimizing the need for substrate polishing (descum) preceeding the plasma process. Etching proceeds by the proven Bosch DRIE switched process for straight profiles using the Mosaic™ platform with Rapier™-S modules as produced by SPTS.[3] Plasma etch selectivity for silicon vs. erosion of Daetec's washable coatings as Si:mask, is observed to be 1,000:1, or greater.4 The process is finished with simple DIW rinsing, leaving the surface free of residue and ready for die pickup. This paper presents further details on plasma dicing using water washable coatings.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128502931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process and Design Consideration for Wafer-to-Wafer Hybrid Bonding","authors":"I-Ting Wang, K. Chui, Yao Zhu","doi":"10.1109/EPTC47984.2019.9026651","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026651","url":null,"abstract":"In this paper, we evaluate the surface condition with consideration of different process and designed pattern after chemical mechanical polishing (CMP) process in 12-inch platform for high density hybrid bonding application. After the CMP process, the surface topology was carried out by atomic force microscopy (AFM) measurement. We study the impact on the surface topology of the wafer after CMP process, and the results showed that the surface topology including surface roughness and Cu pad dishing/protrusion is dependent on the design of the pad size and spacing and may further make impact on bonding quality, which is needed to be considered carefully.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134594794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enabling Cu Pillar Flip Chip Assembly with Water Soluble Lead-free Solder Paste","authors":"B. S. Kumar, Bayaras Abito Danila, Chong Mei Hoe Joanne, Zhang Rui Fen, S. K. Rath, Chan Li-san, Wong Chin Yeung Jason","doi":"10.1109/EPTC47984.2019.9026676","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026676","url":null,"abstract":"This paper reports the evaluation of printability along with attachment of Copper (Cu) Pillar Flip Chip (FC) and passive component, such as 008004, for the solder paste AP5112 T7. The solder paste can sustain continuous printing up to 8hrs using $70mu mathrm{m}$ stencil opening and $50mu mathrm{m}$ line spacing. The pot-life and shelf-life of the paste have been evaluated to be 72hrs and 4 months, respectively. The solder paste has been designed for use in Systems in Package (SIP) such as components including 008004 and Cu Pillar FC. The advantage of using this paste would be the single step stencil printing process for attachment of both passive(s) and Cu pillar FC, without involving flux dipping/printing. The results indicate the paste is suitable for Cu pillar FC attachment, with <1% voids, enable consistent stand-off heights, with stencil opening, down to 90%. Results using 008004 components show <1% voids, no solder beads and no tombstones.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"14 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132531314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Best Engineering Practices to Establish Cooling Limit for 375W Add-in PCI-e Center Accelerator Card with Active Optical","authors":"G. Refai-Ahmed, Brian Philofsky, V. Gektin, B. Sammakia, Hoa Do, S. Rangarajan","doi":"10.1109/EPTC47984.2019.9026618","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026618","url":null,"abstract":"There are many widely available heat transfer technologies that use forced air and vapor chambers to solve thermal problems up to 40 Watts/cm2. The chart in Figure 1 provides an overview of today's cooling technologies, markets, and total device power in Watts while introducing heat flux limits in W/cm2 for air cooling versus liquid cooling. The present study investigates the characterization of an air-cooled 375 W add-in PCI-e Card with active optical modules based on a computational fluid dynamics (CFD) model at different airflow rates. The numerical model correlates the thermal performance of a FPGA chip with test data from a Dell R740 chassis. Using Ansys IcePak V19.1 software [1], a series of CFD simulations has been performed to determine the temperature and flow fields over a range of airflow rates. In order to validate the computational model findings, experiments were conducted to obtain the airflow and pressure drop values at different flow rates using an Air Movement and Control Association (AMCA) standard wind tunnel. It was determined that the PCI-e card test data correlated with the numerical model and that the limitations of existing air-cooled heatsinks can be extended by including a textured surface as detailed in a patent by Refai-Ahmed et al. [2] on the base of the heatsink. Hence, the thermal interface material (TIM1.5) between the silicon chip and the textured surface can be represented at 70 microns thickness with an effective thermal conductivity of 20 W/m-K which has a higher overall performance.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132259782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of in-plane property variations on warpage shapes of organic substrates","authors":"S. Kohara, K. Okamoto, H. Mori","doi":"10.1109/EPTC47984.2019.9026717","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026717","url":null,"abstract":"The reduction of warpage of organic substrates is one of the challenges in flip chip package applications, since the warpage affects the manufacturability of chip joining and potentially, the solder joint reliability. Mechanical simulation of organic substrates results in a warpage shape that reflects the symmetry of the circuitry pattern, often in a bowl shape, when the circuitry pattern is taken into account. However, the actual substrates manufactured often exhibit warpage shapes that are randomly distorted and are different from each other even when they have identical circuitry design patterns and are segmented from the same panel. Potential causes for the spread in warpage shapes are inhomogeneities in processes or environmental conditions during manufacturing which can lead to an in-plane variation or fluctuation in substrate properties. In this report, the deformation of organic substrates under in-plane variations of substrate properties are analyzed by mechanical simulation. A simple substrate structure with a plane copper and an insulating dielectric layer on both sides of the core layer was used as the model for the analysis. Potential varying properties are material properties such as elastic modulus and coefficient of thermal expansion. The form factors such as layer thicknesses can also vary along the in-plane direction. In our analyses, the in-plane variations as a whole are incorporated in simulation as a change in cure shrinkage rate of insulating dielectric layers in order to generate various warpage shapes. The cure shrinkage rate was used, since it is temperature independent in simulations by finite element method (FEM). Linear variations with lateral length scales of the substrate size are applied. Several configurations of variations are studied by changing the positions of maximums of the cure shrinkage rate. The analyses revealed that the configuration of variations is an important factor in determining the warpage shape of a substrate. The analysis also showed that the balance of property between front layers and back layers of the substrate has a great influence in determining the warpage shapes. The analysis of the in-plane layer thickness variation showed that the magnitude of warpage for insulating dielectric layer is greater than that for the conductive layer. The result suggests that the control of the uniformity of properties and thickness of insulating dielectric layers are important in reducing the warpage caused by inhomogeneity of properties occurring during manufacturing processes. The warpage analysis of the in-plane property variation was also conducted for a test substrate with a 3-2-3 build-up layer structure to examine the effects of in-plane property variation on warpage of patterned substrates. The results showed that the warpage of a substrate with a symmetric circuitry pattern results in an asymmetric shape when an asymmetric in-plane property variation occurs. The warpage caused by circuitry pattern","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128288956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pure silver wire bonding on palladium finishing for automotive application","authors":"Riccardo Villa, N. Hashim, Darwin BINI, Ivana Favretto","doi":"10.1109/EPTC47984.2019.9026677","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026677","url":null,"abstract":"Material selection in wire bonding requires the best match of electrical characteristics, mechanical properties and material cost to reach high performance and competitiveness in automotive market. Silver alloy is emerging to replace gold and copper thanks to its softness, however it reveals high resistivity when bigger wire diameter is needed for high current applications. The aim of this work is to introduce pure silver wire bonding on palladium finished pads as new alternative able to combine low electrical resistivity and excellent reliability performance. For this purpose, process capability and reliability tests outcome are reported to characterize the new material during product operating life.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126200657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Creep Damage of BGA Solder Interconnects Subjected to Thermal Cycling and Isothermal Ageing","authors":"Joshua A. Depiver, S. Mallik, D. Harmanto, E. Amalu","doi":"10.1109/EPTC47984.2019.9026710","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026710","url":null,"abstract":"Solder joints of electronic components are the most critical part of any electronic device. Their untimely failure during the system's operation often culminates in catastrophic failure of the device. The determination of creep damage in electronic component solder joint is vital to the prediction of crack initiation and prevention of premature failure. This paper presents the creep damage in solder joints in a ball grid array (BGA) soldered on a printed circuit board (PCB) and subjected to thermal cycling as well as isothermal ageing. ANSYS 19.0 package is employed to model the isothermal ageing at −40, 25, 75 and 150°C temperatures for 45 days. Standard temperature cycle profile is used to simulate the effect of the coefficient of thermal expansion (CTE) mismatch on the bonded materials in the BGA component. The solders studied are lead-based eutectic solder alloy and lead-free SAC396, SAC387, and SAC305. Based on the results obtained for the stress, strain rate, deformation rate and strain energy of the solders, the research investigation advises on the most effective solder for achieving improvement in the thermo-mechanical reliability of solder joints in BGA soldered on PCB.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127237787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhance Larger FCBGA Package Evaluation and Characterization","authors":"V. Lin, N. Kao, David Lai, D. Jiang","doi":"10.1109/EPTC47984.2019.9026653","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026653","url":null,"abstract":"In order to enable higher electrical performance for the application of networking, larger FCBGA package was been demanded to meet the electrical target. According to that, the package size usually has been kept to be large around 60mm x 60mm and die size has been larger than 20mm x 20mm in advance networking application. Normally, larger FCBGA package would result in increased semiconductor assembly processes and reliability challenges, such as die corner delam, solder mask crack, Cu post side wall delam, TIM coverage loss and warpage issue. Molded type FCBGA package would be a solution to reduce processes and reliability risk. Several Molded type FCBGA packages were proposed in this paper to check the level of stress and warpage performance compared to traditional EHS-FCBGA package. Regarding solder mask crack, ABF substrate structure will be the suggestion to avoid solder mask crack issue. According lots fundamental work, molded type FCBGA package combined ABF substrate could reduce package stress effectively and perform similar warpage with traditional EHS-FCBGA to be a solution to solve current larger FCBGA package processes and reliability issue.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128525933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quality of pressure sintering","authors":"M. H. Koelink, J. Hamelink","doi":"10.1109/EPTC47984.2019.9026696","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026696","url":null,"abstract":"Pressure sintering is relatively new joining technology with very good performance and reliability, making it the technology of choice for automotive power electronics. But the automotive industry demands high quality and reliability and this drives research into better understanding of parameters that influence reliability and failure mechanisms, in order to control quality. In this paper we present an overview of the currently known parameters that influence the quality as well as a number of (potential) measurement and inspection systems that quantify leading and indicative parameters for quality and reliability.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125964889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}