2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)最新文献_第9页

Thermal Characteristic Evaluation of Silver and Copper Sintering Materials 银和铜烧结材料的热特性评价

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026702

K. Murayama, H. Ota, K. Oi

{"title":"Thermal Characteristic Evaluation of Silver and Copper Sintering Materials","authors":"K. Murayama, H. Ota, K. Oi","doi":"10.1109/EPTC47984.2019.9026702","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026702","url":null,"abstract":"In recent years, the demand for power modules has increased rapidly. Sintering materials for die attaching has received remarkable attention from power module industry. Sintering techniques are required to realize for high reliability bonding for wide band gap (WBG) device such as SiC and GaN device. However, their reliability and knowledge of thermal characteristic depends on die attaching material have been a little investigated. In this study, we will discuss difference of thermal characteristic among silver sintering material, copper sintering materials and high lead solder. TO-247 type molded packages were employed for evaluation of die attaching materials. Change in transient thermal resistance were measured after thermal cycling test by T3Ster. The thermal resistance of die attaching portion were analyzed by structure functions. Simulations of transient thermal resistance were performed on the effects of various parameters of the constituent materials on the structure function. The die attach portion of structure function was specified from the simulation. These results indicate that thermal resistance of silver sintering material and copper sintering material portion are lower than that of high lead solder portion and crack resistivity of silver sintering material and copper sintering material are higher than that of high lead solder.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131383639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Effect of Cryogenic Temperature on Mechanical Fracture mechanism of Cu/Sn3.0Ag0.5Cu-Solder/Cu Joint 低温对Cu/Sn3.0Ag0.5Cu-Solder/Cu接头力学断裂机制的影响

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026699

Xingguo Fu, Si Chen, Yun Huang, Bin Yao, R. Yao, Bin Zhou

引用次数: 1

Development of FCBGA substrate with low Dk/Df material based on automotive reliability conditions 基于汽车可靠性条件的低Dk/Df材料FCBGA衬底的研制

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026708

ShinKi Lee, Han-Chil Lee, Hunju Lim, Inseok Hwang, Wooyong Jung, ChangWon Ma, DongSu Lee, Younho Jung, D. Lee, Sangwoo Han, E. Ahn, Young-Hwan Shin

引用次数: 3

Ultra Low Profile Power Inductor Integrated in Wafer Level Package 超低轮廓功率电感集成在晶圆级封装

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026645

Yu-Chang Hsieh, Shiuan-Yu Lin, C. Kung, Pao-Nan Lee, Chen-Chao Wang

引用次数: 1

Investigation on Thermal Contact Resistance Between Indium and Cap in Packaging 包装中铟与瓶盖热接触阻的研究

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026694

Jianxiong Hu, Zefang Fengchen, Ye Zhang, Yixin Xu, F. Zhu

引用次数: 1

Void Formation in Low-Temperature Electroplated Cu-Sn Stack for Hermetic Packaging 密封封装用低温电镀铜锡堆中空隙的形成

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026664

H. K. Kannojia, P. Dixit

{"title":"Void Formation in Low-Temperature Electroplated Cu-Sn Stack for Hermetic Packaging","authors":"H. K. Kannojia, P. Dixit","doi":"10.1109/EPTC47984.2019.9026664","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026664","url":null,"abstract":"Electrodeposited Cu-Sn based solid-liquid interdiffusion (SLID) bonding is a popular technique used for the hermetic encapsulation in various MEMS applications. However, the micro-void formation remains a serious problem that critically degrades the bond strength and the long–term reliability of the MEMS devices. In this study, the void formation and intermetallic growth in electrodeposited Cu-Sn stack layer at temperatures below and above the melting point of tin, i.e., 232 °C are reported. The samples were fabricated on 2-inch silicon substrates using standard microfabrication techniques. Voids were observed to be larger in samples annealed at temperatures above the melting point of tin. This was due to the enhanced Kirkendall's effect as well as higher dissociation and segregation of incorporated impurities in the electrodeposited metals at higher processing temperatures. Successful bonding of electrodeposited tin over the copper pad (bottom-side) to the bare copper pad (top-side) was demonstrated at low temperature, i.e., 150 °C with the minimum voids at bond interfaces and within the intermetallic compounds.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128371926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Low-Cost Chip2Chip Integration for Partitioning Processing and Memory 用于分区处理和内存的低成本芯片集成

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026691

Fabian Hopsch, A. Heinig

引用次数: 0

Electrical Performance Evaluation of a Gripper-Type Socket Technology 一种夹持式插座技术的电气性能评价

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9076728

Emad S. Al-Momani, S. Harb, Kyle Tripician, Rajaa Alqudah

引用次数: 0

Development of 2.5D high density device on large ultra-thin active interposer 大型超薄有源中间体上2.5D高密度器件的研制

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026720

S. Lim, V. Chidambaram, N. Jaafar, W. Seit

{"title":"Development of 2.5D high density device on large ultra-thin active interposer","authors":"S. Lim, V. Chidambaram, N. Jaafar, W. Seit","doi":"10.1109/EPTC47984.2019.9026720","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026720","url":null,"abstract":"In the recent years, the industry is moving towards finer, higher density interconnections and better electrical performance from the die to the substrate. The 3D stack assembly using through silicon via (TSVs) has been emerging as a good solution by using heterogeneous technologies. By stacking the ICs heterogeneously, TSV technologies can allow for faster electrical performance with little signal propagation time delay, consumes less power and smaller foot prints. In addition, the TSV technology also removes the using of substrate at finer pitch and integrate high power performance interconnects functions for chip-to-chip communication [1]. The work presented in this paper highlights the assembly challenges in the attachment process of the chip-on-chip substrate package onto the large $150mu mathrm{m}$ pitch Via-Last TSVs interposer at $40mu mathrm{m}$ thickness. The top level design consists of an FPGA (28nm, 12.65 m x 12.34 mm size, Arria V programmable SoC), two IO chips (65nm, 4mmx 4mm, Split IO and ESD) flip chip attached to a 130nm active through silicon interposer with dimension 22.8 mm x 16.4 mm. In summary, the method of handling such a thin large active interposer at 40um poses many challenges in the TSV assembly. A different assembly approach is required to ensure minimum silicon interposer warpage and allows for good SnAg solder formation and wetting for both the FPGA die and the 65nm dies during reflow process. Detailed underfill process optimization needs to be studied to achieve no voids in the Fine pitch interconnect assembly on large active silicon interposer. The assembled ATSI package is able to pass with good electrical continuity results for 3 different reliability tests.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125908699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Soldering Material Evolution for Heterogeneous Integration 异质集成焊接材料的演变

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026658

K. Thum, S. Lim

引用次数: 1