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2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)最新文献

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Multiphysic Simulations for MEMS Sensor Package MEMS传感器封装的多物理场仿真
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026616
M. Del Sarto, R. Duca, A. Maierna, N. Manca, M. O. Ghidoni, T. Napolitano
{"title":"Multiphysic Simulations for MEMS Sensor Package","authors":"M. Del Sarto, R. Duca, A. Maierna, N. Manca, M. O. Ghidoni, T. Napolitano","doi":"10.1109/EPTC47984.2019.9026616","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026616","url":null,"abstract":"Presence of sensor is relevant reality on all aspects of human life and based on the development of Internet of Things (IoT) in recent years the presence of sensors in our daily life is expected to continue increasing. The usability of a sensor in an application is derived from its technical performance but hardly driven from the package design to fit the system. Also cost down roadmap of MEMS based sensor is driving to study new solution to be able to use, for example, consumer market based material for automotive solutions. In this paper we will present an overview of different techniques based on FEM modeling used for virtual characterization, comparative and predictive design used for MEMS based sensor and microsystem modules. The target is to provide a toolbox for package designers at an early stage of product development targeting a design where package is functional part of the device.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125227037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Socket Signal Integrity Assessment for High Speed LPDDR4 Memory Test Applications 高速LPDDR4内存测试应用的插座信号完整性评估
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9076717
S. Harb, Emad S. Al-Momani, Bong-Seon Yu, Rajaa Alqudah
{"title":"Socket Signal Integrity Assessment for High Speed LPDDR4 Memory Test Applications","authors":"S. Harb, Emad S. Al-Momani, Bong-Seon Yu, Rajaa Alqudah","doi":"10.1109/EPTC47984.2019.9076717","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9076717","url":null,"abstract":"As the data rate of Low Power Double Data Rate 4 (LPDDR4) memory is reaching higher speeds, it is becoming more crucial to evaluate and assess the electrical performance of the viable socket technologies in the market. This paper presents a signal integrity (SI) evaluation for gripper-type pin technology, one of the commercially available socket technologies which potentially can be enabled for high speed LPDDR4 memory test applications with a data transmission rate of up to 2.4 Gb/s. We performed three-dimensional numerical simulations with a commercially available 3D FEM (finite element method)-based full-wave software package (Ansoft HFSS). We evaluated No-Socket vs. Single-Sided gripper socket pins and compared their signal transmission characteristics. Simulation results showed that the worst case margin degradation for the single-sided gripper socket could be improved by reducing the Z-axis height of the socket pin to minimize crosstalk and achieve better performance at higher GHz frequencies.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116112919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the Elimination of Die Attach Defects Occurrence - Optimization of Silver Sinter Curing Profile Using Simultaneous Thermal Analyses 消除模具附着缺陷的研究——利用同步热分析优化银烧结料的固化轮廓
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026711
Marty Lorgino D. Pulutan, Bobby Johns L. Villacarlos
{"title":"On the Elimination of Die Attach Defects Occurrence - Optimization of Silver Sinter Curing Profile Using Simultaneous Thermal Analyses","authors":"Marty Lorgino D. Pulutan, Bobby Johns L. Villacarlos","doi":"10.1109/EPTC47984.2019.9026711","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026711","url":null,"abstract":"This study aims to utilize Simultaneous Thermal Analysis - Differential Scanning Calorimetry (DSC) and Thermogravimetric Analysis (TGA), along with respective differential curves to infer relative data points such as temperature and shape of peaks, duration and percentage of solvent outgassing to design and optimize curing profile with appropriate outgassing and sintering time and temperature, ramp up rate at shortest duration. Using different scan modes; isothermal and dynamic, five different curing profiles were derived and simulated to check thermal responses. The effectiveness of each profile was evaluated through curing of die-attached units and the presence of die bulging and channeling voids were assessed through five-point Bondline Thickness (BLT), SEM and SCAT. It was found out that gradual solvent outgassing at lower temperature and longer time, as well as choosing lower sintering temperature and ramp-up rate could prevent formation of these anomalies. It was also proven that unoptimized curing profile triggers the occurrence and recurrence of die bulging and channeling voids.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128356260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigation of Liquid Cooling for Data Center Server Based on Micro-fluid Technology 基于微流体技术的数据中心服务器液冷研究
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026695
Yong Han, B. L. Lau, G. Tang, Haoran Chen, S. Lim, Xiaowu Zhang
{"title":"Investigation of Liquid Cooling for Data Center Server Based on Micro-fluid Technology","authors":"Yong Han, B. L. Lau, G. Tang, Haoran Chen, S. Lim, Xiaowu Zhang","doi":"10.1109/EPTC47984.2019.9026695","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026695","url":null,"abstract":"As rapid development of cloud computing, Internet of things, and artificial intelligence, the requirement of computing capability is increasing significantly, spurring tremendous evolution and exponentially growth of modern data centre. To address the thermal issue and save energy cost, a liquid cooling solution based on micro-fluid technology has been developed for server to enable high heating power dissipation on board. Experimental test is performed on the server board with both thermal chips being heated up with gradually increased power, and the liquid cooling modules are connected in different ways for characterization. Heat dissipation capability of >150W per chip has been demonstrated. The thermal performance by using the liquid cooling has been investigated and compared. Low cooling energy consumption is needed to achieve stable cooling performance. The developed liquid solution based on micro-fluid technology shows guarantee to enable the potential capability of advanced servers in future data center.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128613474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Simulation and experimental study on chip module warpage by digital image correlation 芯片模块翘曲的数字图像相关仿真与实验研究
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026679
Licheng Wang, Sheng Liu, Zhiwen Chen
{"title":"Simulation and experimental study on chip module warpage by digital image correlation","authors":"Licheng Wang, Sheng Liu, Zhiwen Chen","doi":"10.1109/EPTC47984.2019.9026679","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026679","url":null,"abstract":"In this paper, warpage experiment was carried out on electronic module in heating process by the digital image correlation. As a widespread used measurement in recent years, digital image correlation technology was used in the electronic packaging for measuring warpage and its strain. DIC includes two key steps: camera calibration and image matching. The camera calibration involves a pinhole model approach. It employs feature-matching-based initial guess, multiple subsets, iterative optimization algorithm, and reliability-guided computation path to achieve fast and accurate image matching. Image matching process was calculated by software Vic-3D. Simulation have been conducted to verify the experimental results by Abaqus. By comparing the results of experiment and simulation, the measurement results for chip's warpage are correct.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128984443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Planar Circularly Polarized Antenna for UWB High Band Applications 用于超宽带高频段的平面圆极化天线
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026621
Shunsuke Kai, H. Kanaya
{"title":"Planar Circularly Polarized Antenna for UWB High Band Applications","authors":"Shunsuke Kai, H. Kanaya","doi":"10.1109/EPTC47984.2019.9026621","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026621","url":null,"abstract":"In this paper, we propose the design of $1times 2$ array circularly polarized (CP) slot antenna for UWB High band applications. The proposed antenna element is composed of three parts: a top metal that consists of L-shaped slot structure, a dielectric substrate (FR4), and a bottom floating metal layer. To realize a high gain toward the z-axis direction, the two antenna elements are arrayed, and each antenna is connected with the branched CPW (coplanar wave guide) transmission line. The simulated results of S-parameter, axial ratio, and the antenna gain of the $1times 2$ array antenna are presented. The operation bandwidth of the proposed antenna is 1.10 GHz (9.35 GHz–10.45 GHz), and the relative bandwidth is 11.1%. The peak gain is 6.05 dBic at 9.9 GHz.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130419746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Die Sticking Quality Issue of Tape-and-Reel Packaging for WLCSP WLCSP卷带包装粘模质量问题
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026568
L. Khine, Joel C. Alimagno
{"title":"Die Sticking Quality Issue of Tape-and-Reel Packaging for WLCSP","authors":"L. Khine, Joel C. Alimagno","doi":"10.1109/EPTC47984.2019.9026568","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026568","url":null,"abstract":"Various factors could deteriorate the quality of Tape-and-Reel (TnR) packaging for Wafer-level Chip Scale Package (WLCSP) devices, of which “die sticking onto cover tape” issue found during die pick-up from the pocket or carrier tape during the Surface-mount Technology (SMT) process is a serious real-world challenge. If TnR packaging process is not carefully designed and monitored, such die sticking events would significantly slow down die pick-up throughput, and millions of units could be placed on hold by end customer, with serious financial ramifications. A series of design of experiments (DOEs) were carried out, as a collaboration between ADI and UTAC, to explore this die sticking phenomenon. Based on lessons learned from production runs of WLCSP devices, along with the results of the DOEs as presented in this paper, new and improved Tape-and-Reel packaging design guidelines were formulated for preventing the occurrence of die sticking issue.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"13 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123516821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Failure detection technique for 2/2um RDL on FOPLP FOPLP上2/2um RDL故障检测技术
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026657
K. Gunji, N. Takagi, Toshibisa Hibarino
{"title":"Failure detection technique for 2/2um RDL on FOPLP","authors":"K. Gunji, N. Takagi, Toshibisa Hibarino","doi":"10.1109/EPTC47984.2019.9026657","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026657","url":null,"abstract":"This paper introduces the test technology of redistribution layer used in FOPLP. In order to lower costs, FOPLP needs to adopt the RDL first process. In addition, it is necessary to guarantee that the package such as 2.5D that formed RDL is non-defective before mounting ICs. Since RDL is mounted on a carrier such as glass, double-sided inspection of the package becomes difficult. It is capacity inspection that can be proposed as this solution. In our work, we have improved the micro capacity tester to the accuracy below femto farad. Using this tester, we have demonstrated defect detection between RDL vias, formation defects of plating etc., in the package manufactured in an actual process. This method also allowed us to consolidate probing on one side. We introduce technologies for solving 40 um fine pitched micro pad probing problems as well as achieving a lower cost of test for a line and space 2/2 um FOPLP.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124453467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Solution of Design Induced Reliability Risk for High Density Fan-Out packages 高密度扇出封装设计诱发可靠性风险的求解
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026715
Yu-Ting Lin, Yi-Sheng Lin, Yu-Hsiang Hsiao
{"title":"Solution of Design Induced Reliability Risk for High Density Fan-Out packages","authors":"Yu-Ting Lin, Yi-Sheng Lin, Yu-Hsiang Hsiao","doi":"10.1109/EPTC47984.2019.9026715","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026715","url":null,"abstract":"Fan-Out (FO) technologies are used for consumer electronic products generally due to the small and very thin features. Some risks would be found when the design transfer from of 2.5D Integrated Circuit (2.5D IC) or system in packages (SiPs) to the FO packages. This paper will share a case study of High Density Fan-Out (HDFO) with thermal cycle test (TCT) and the test vehicle is open/short fail. The test vehicle is examined by curve tracer (I-V), 3D X-ray, Focus Ion Beam (FIB) and Scanning Electron Microscope (SEM) to find out the failure mode. The failure mode is delamination between the u-pad layer and the Redistribution Layer (RDL) interface. The Cu oxide layer is found on the RDL sidewall. The chemical residue leads to the oxidation of Cu on the RDL surface and the poor interface would be delamination gradually during TCT. Root cause of the chemical residue was investigated in this study. The delamination issue was resolved by adding plasma clean.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127748292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experimental Study of Single-Phase Cooling with DI Water in An Embedded Microchannels-3D Manifold Cooler 嵌入式微通道-三维流形冷却器DI水单相冷却实验研究
2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026600
K. Jung, Feng Zhou, M. Asheghi, E. Dede, K. Goodson
{"title":"Experimental Study of Single-Phase Cooling with DI Water in An Embedded Microchannels-3D Manifold Cooler","authors":"K. Jung, Feng Zhou, M. Asheghi, E. Dede, K. Goodson","doi":"10.1109/EPTC47984.2019.9026600","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026600","url":null,"abstract":"We report on an advanced cooling Embedded Microchannels-3D Manifold $mu$-Cooler (EMMC) capable of removing heat fluxes ∼1 kW/cm2, at a junction temperature ∼ 100–120 °C, with thermal resistance of ∼0.1 cm2-K/W, and pressure drop up to 8.4 kPa at flow rate of 200 g/min using single-phase DI water at the inlet temperature of 25 °C. The proposed EMMC design consists of two substrates: a microchannel cold-plate that is etched in to the silicon chip, and a fluid-routing silicon-based 3D manifold that delivers the cold liquid and extracts the hot fluid from the microprocessor. The EMMC consists of 25 parallel microchannels with a cross-sectional area of $75 times 150 mu mathrm{m}^{2}$ that are embedded into the cold-plate. The fluid-routing manifold bonded to the cold-plate has four inlet and five outlet conduits with channel heights of 700 and $1000 mu mathrm{m}$, respectively. A gold serpentine heater is defined in a 52 mm2 of hotspot area located at the center of the cold-plate top surface that supplied heat fluxes from 50 to 900 W/cm2. The heated surface temperature is monitored by Infrared (IR) camera in real-time along with the electrical resistance thermometry.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"IA-11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126555357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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