2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)最新文献_第2页

Modelling and characterization on wafer to wafer hybrid bonding technology for 3D IC packaging 三维集成电路封装晶圆间混合键合技术的建模与表征

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026578

L. Ji, F. Che, H. Ji, H.Y. Li, M. Kawano

引用次数: 12

Hybrid Sintering Glue and Stencil Printing Process: New Generation Die Attach Method for Quad Flat No Leads Package 混合烧结胶和模板印刷工艺:新一代四平无引线封装的模具贴装方法

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026684

B. C. Bacquian

引用次数: 0

Study on Stress and Reliability of Advanced Intelligent Power Module (IPM) Subjected to Power Cycling 功率循环作用下先进智能电源模块(IPM)的应力与可靠性研究

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026668

F. Che, Kazunori Yamamoto, G. Tang, L. Ji

引用次数: 0

Determination of the Complex Thermal Characteristics of Discrete Power Devices and Power Modules 离散功率器件和功率模块复杂热特性的测定

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026589

M. Rencz, A. Poppe, G. Farkas

引用次数: 0

Epoxy Mold Compound Characterization and Cure Kinetics for Post Mold Isothermal Cure Improvement and Accelerated Reliability Assessment 用于模后等温固化改进和加速可靠性评估的环氧模复合材料表征和固化动力学

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026594

Matthew M. Fernandez, Beila Angeles, Deo Navaja

引用次数: 2

Innovative Approach of efficient low-temperature silver sintering on an industrial series scale for simultaneous die top and bottom level interconnections of power electronic applications 高效低温银烧结工业系列规模的创新方法，同时用于电力电子应用的上下级互连

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026636

M. Mueller, J. Franke

{"title":"Innovative Approach of efficient low-temperature silver sintering on an industrial series scale for simultaneous die top and bottom level interconnections of power electronic applications","authors":"M. Mueller, J. Franke","doi":"10.1109/EPTC47984.2019.9026636","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026636","url":null,"abstract":"In recent years, the number of power electronic assemblies has increased significantly both in products and machines for the end user and in products and machines for industry. Above all, however, power electronics is becoming more and more important in drive technology and the generation of renewable energies. Power electronic modules, such as inverters and rectifiers or DC converters, are required to provide more and more power in the advancing field of electromobility, while the installation space is constantly being reduced. At the same time, however, these assemblies must have the longest possible and most reliable lifetime. Previous power electronic modules have a maximum junction temperature of 150 °C due to the materials used in assembly and connection technology. New types of wide band gap semiconductors, however, already offer the possibility of enabling junction temperatures of 200 °C and above. The aim of the investigations in this paper is to qualify a sintering process that is suitable for efficient series production for an all-in-one joining process in assembly and interconnection technology. By replacing the solder layer with a silver sinter paste, operation at junction temperatures significantly above 150 °C is possible. However, if the maximum junction temperature is maintained at the current level of 150 °C, higher reliability and longer lifetime of the power electronic modules are expected. In active power cycling tests, the reliability of the demonstrators produced in the series sintering process is compared with the service life of soldered reference samples.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130083473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal and Mechanical Analysis of Imaging Ball Grid Array Image Sensor Package 成像球栅阵列图像传感器包的热力学分析

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026648

Ying Jia, K. L. Kyaw, Teddy Joaquin Carreon

{"title":"Thermal and Mechanical Analysis of Imaging Ball Grid Array Image Sensor Package","authors":"Ying Jia, K. L. Kyaw, Teddy Joaquin Carreon","doi":"10.1109/EPTC47984.2019.9026648","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026648","url":null,"abstract":"The growing demand of mobile phone, cameras and automotive pushes development of image sensor packaging in a trend of shrank form factor and more complex substrate design. To cater to the demand, the next generation image sensor package, Imaging Ball Grid Array (iBGA), was developed by UTAC. iBGA packages use organic substrates instead of ceramic carrier used in previous image sensor packages, for example, CLCC (Ceramic Leadless Chip Carrier) package. iBGA allows image sensor to become smaller, more advanced routings and alternative bill of materials to address specific material lead-times. When a new packaging is developed, characterizations of the package are crucial. Finite element modeling and simulation approach is proven to be the most efficient and enable shorter time to market by elimination numerous engineering DOE and design-prototype-test cycles. Firstly, for any IC packaging, thermal performance is one of the factors needs to be considered as the new packaging type should not be so warm that will have negative impact on overall performance and reliability of the device. Secondly, as image sensor's essential part is a glass and glass is a brittle material, thermo-mechanical stress due to CTE miss-match to be resolved when developing the package. In this paper, the characterization of UTAC image sensor package imaging ball grid array (iBGA) is studied. The structure and the packaging process of iBGA are illustrated. Thermal simulation is done using Computational Fluid Dynamic (CFD) simulation software to study heat dissipation and thermal performance under steady state condition with JEDEC standard. Moreover, mechanical simulation for warpage is conducted using Finite Element Analysis (FEA) simulation tool and correlated with Shadow Moiré measurement. Lastly, reliability examination is also done for iBGA. Studies will reveal the mechanical characteristics and thermal performance of the package in depth.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134062030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Thermal simulation and measurement of SiC MOSETs SiC moset的热模拟与测量

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026682

Jung Kyun Kim

{"title":"Thermal simulation and measurement of SiC MOSETs","authors":"Jung Kyun Kim","doi":"10.1109/EPTC47984.2019.9026682","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026682","url":null,"abstract":"This paper shows that thermal characterization of SiC MOSFETs module using the thermal transient measurement method, simulation, and calibration. To determine the thermal resistance values of the junction-to-case (RthJ-C), the JEDEC JESD 51-14 transient dual interface measurement method is a well-known and industry-wide accepted technique. In this article we also show a thermal model calibration tasks using transient thermal measurement for even more accurate thermal simulations and improve the reliability of components. The ability to find a measurable structure allows us to create a simulation model of the package and calibrate it against the measured thermal signal. The calibration process started with a thermal transient test to obtain the behavior of the selected semiconductor component, in our case the average temperature on the volume region of die. Important calibration parameters we investigated was the absolute size of die, thermal conductivity of die attach solder, substrate, ceramic, cold plate and contact resistance of base plate and cold plate. Calibrated structure function of SiC Schottky diode had matched with measured structure function with accuracy 99.89 % and calibration extent 0.85 K/W.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134261879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Effect of the Curing properties and Viscosities of Non-Conductive Films (NCFs) On Ultra-Fine Pitch Cu-pillar/Sn-Ag Bump Joint Morphology and Reliability 非导电膜的固化性能和粘度对超细节距铜柱/锡银碰撞接头形貌和可靠性的影响

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026692

Hanmin Lee, Taejin Choi, SooIn Park, K. Paik

{"title":"Effect of the Curing properties and Viscosities of Non-Conductive Films (NCFs) On Ultra-Fine Pitch Cu-pillar/Sn-Ag Bump Joint Morphology and Reliability","authors":"Hanmin Lee, Taejin Choi, SooIn Park, K. Paik","doi":"10.1109/EPTC47984.2019.9026692","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026692","url":null,"abstract":"In this study, flip chip assembly using NCFs was evaluated for ultra-fine pitch Cu-pillar/Sn-Ag bumps. The $4 text{mm} times 4 text{mm}$ size Si chips had $32 mu mathrm{m}$ height and $20 mu mathrm{m}$ diameter Cu-pillar/Sn-Ag micro bumps, and the bump pitch was $30 mu mathrm{m}$. And $12 text{mm} times 12 text{mm}$ size printed circuit boards (PCBs) had $23 mu mathrm{m}$ width Cu pads and organic solder-ability preservative (OSP) surface finishes. Solder joint morphology was evaluated and optimized by adjusting the curing properties such as curing onset, peak temperature and the viscosities of NCFs by changing curing agents and silica contents. And then, in order to understand changes of solder joint morphology during flip chip bonding process, solder joint was also evaluated depending on flip chip bonding times and temperatures. Based on the results, it was confirmed that solder joint morphology is determined at solder melting temperature of 221°C. And then, degree of cure and viscosity approximation was conducted to define the precise viscosity of NCFs at the solder melting temperature using measured degrees of cure at various bonding temperatures. As a result, concave shaped solder joint and NCFs trap were generated between 545,140 and 551,007 Pa·s of NCFs viscosity at solder melting temperature. Finally, high temperature and high humidity (85RH%/85°C) test, temperature cycling (T/C) test is performed to evaluate the hygroscopic and thermo-mechanical reliability performance depending on solder joint morphology. The reliability test results showed stable electrical resistance changes within 10% of average value.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134379993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An LTCC Based H-Antenna Aperture Coupled to an On-Chip Antenna for 2.4 GHz Long Range Transmitters

2019 IEEE 21st Electronics Packaging Technology Conference (EPTC) Pub Date : 2019-12-01 DOI: 10.1109/EPTC47984.2019.9026590

S. Archana, M. Bhaskar

{"title":"An LTCC Based H-Antenna Aperture Coupled to an On-Chip Antenna for 2.4 GHz Long Range Transmitters","authors":"S. Archana, M. Bhaskar","doi":"10.1109/EPTC47984.2019.9026590","DOIUrl":"https://doi.org/10.1109/EPTC47984.2019.9026590","url":null,"abstract":"Package antennas designed at lower GHz frequencies and aperture coupled to on-chip antennas help to provide fully integrated System-in-Package transmitters with high gain, efficiency and lower power consumption. In this paper, a superstrate H-antenna with H-shaped ground plane is used as a package antenna which provides high gain and miniaturization. The package antenna is aperture coupled to a two-turn on-chip loop antenna, which is conjugately matched to a differential Class-E power amplifier (PA) with current reuse. The PA, along with the antenna system, helps to increase the communication range of transmitter. PA and on-chip antenna are designed in UMC 180nm technology, while the package antenna is designed in Low Temperature Co-fired Ceramic (LTCC) package. From the post-layout simulations performed in Cadence virtuoso, the PA has a maximum output and power added efficiency (PAE) of 19 dBm and 50%. H-antenna and loop antenna are simulated in Advanced Design System (ADS). From the simulations, the on-chip loop antenna has a gain and efficiency of −20.5 dBi and 0.42%. The aperture coupled H-antenna has a gain and efficiency of −1.6 dBi and 17.2%. The proposed design has higher gain and smaller size compared to the design proposed in literature, hence can be used for long range wireless applications.","PeriodicalId":244618,"journal":{"name":"2019 IEEE 21st Electronics Packaging Technology Conference (EPTC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131018342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0